parent
ad84f3a7b3
commit
0915731a9d
17 changed files with 856 additions and 379 deletions
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@ -269,11 +269,11 @@ namespace ARMeilleure.CodeGen.X86
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{
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if (dest.Type == OperandType.I32)
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{
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context.Assembler.Movd(dest, source); // int _mm_cvtsi128_si32
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context.Assembler.Movd(dest, source); // int _mm_cvtsi128_si32(__m128i a)
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}
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else /* if (dest.Type == OperandType.I64) */
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{
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context.Assembler.Movq(dest, source); // __int64 _mm_cvtsi128_si64
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context.Assembler.Movq(dest, source); // __int64 _mm_cvtsi128_si64(__m128i a)
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}
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}
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else
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@ -305,6 +305,26 @@ namespace ARMeilleure.CodeGen.X86
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break;
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}
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case IntrinsicType.BinaryGpr:
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{
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Operand dest = operation.Destination;
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Operand src1 = operation.GetSource(0);
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Operand src2 = operation.GetSource(1);
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EnsureSameType(dest, src1);
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if (!HardwareCapabilities.SupportsVexEncoding)
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{
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EnsureSameReg(dest, src1);
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}
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Debug.Assert(!dest.Type.IsInteger() && src2.Type.IsInteger());
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context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src2.Type);
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break;
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}
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case IntrinsicType.BinaryImm:
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{
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Operand dest = operation.Destination;
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@ -1070,11 +1090,11 @@ namespace ARMeilleure.CodeGen.X86
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if (source.Type == OperandType.I32)
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{
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context.Assembler.Movd(dest, source);
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context.Assembler.Movd(dest, source); // (__m128i _mm_cvtsi32_si128(int a))
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}
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else /* if (source.Type == OperandType.I64) */
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{
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context.Assembler.Movq(dest, source);
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context.Assembler.Movq(dest, source); // (__m128i _mm_cvtsi64_si128(__int64 a))
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}
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}
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