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Add Sqdmulh_S, Sqdmulh_V, Sqrdmulh_S, Sqrdmulh_V instructions; add 6 Tests. Now all saturating methods are on ASoftFallback. (#334)

Browse source 
* Update Instructions.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdHelper.cs

* Update ASoftFallback.cs

* Update CpuTestAlu.cs

* Update CpuTestAluImm.cs

* Update CpuTestAluRs.cs

* Update CpuTestAluRx.cs

* Update CpuTestBfm.cs

* Update CpuTestCcmpImm.cs

* Update CpuTestCcmpReg.cs

* Update CpuTestCsel.cs

* Update CpuTestMov.cs

* Update CpuTestMul.cs

* Update Ryujinx.Tests.csproj

* Update Ryujinx.csproj

* Update Luea.csproj

* Update Ryujinx.ShaderTools.csproj

* Address PR feedback (further tested).

* Address PR feedback.
This commit is contained in:
LDj3SNuD 2018-08-10 19:27:15 +02:00 • committed by gdkchan
parent 267af1f0f7
commit 02a6fdcd13
21 changed files with 834 additions and 314 deletions
Download patch file Download diff file Expand all files Collapse all files

2
Ryujinx.Tests/Cpu/CpuTestAlu.cs
View file

@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
[Category("Alu"), Ignore("Tested: first half of 2018.")]
[Category("Alu"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestAlu : CpuTest
{
#if Alu

2
Ryujinx.Tests/Cpu/CpuTestAluImm.cs
View file

@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
[Category("AluImm"), Ignore("Tested: first half of 2018.")]
[Category("AluImm"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestAluImm : CpuTest
{
#if AluImm

2
Ryujinx.Tests/Cpu/CpuTestAluRs.cs
View file

@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
[Category("AluRs"), Ignore("Tested: first half of 2018.")]
[Category("AluRs"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestAluRs : CpuTest
{
#if AluRs

2
Ryujinx.Tests/Cpu/CpuTestAluRx.cs
View file

@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
[Category("AluRx"), Ignore("Tested: first half of 2018.")]
[Category("AluRx"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestAluRx : CpuTest
{
#if AluRx

2
Ryujinx.Tests/Cpu/CpuTestBfm.cs
View file

@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
[Category("Bfm"), Ignore("Tested: first half of 2018.")]
[Category("Bfm"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestBfm : CpuTest
{
#if Bfm

2
Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs
View file

@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
[Category("CcmpImm"), Ignore("Tested: first half of 2018.")]
[Category("CcmpImm"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestCcmpImm : CpuTest
{
#if CcmpImm

2
Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs
View file

@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
[Category("CcmpReg"), Ignore("Tested: first half of 2018.")]
[Category("CcmpReg"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestCcmpReg : CpuTest
{
#if CcmpReg

2
Ryujinx.Tests/Cpu/CpuTestCsel.cs
View file

@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
[Category("Csel"), Ignore("Tested: first half of 2018.")]
[Category("Csel"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestCsel : CpuTest
{
#if Csel

2
Ryujinx.Tests/Cpu/CpuTestMov.cs
View file

@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
[Category("Mov"), Ignore("Tested: first half of 2018.")]
[Category("Mov"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestMov : CpuTest
{
#if Mov

2
Ryujinx.Tests/Cpu/CpuTestMul.cs
View file

@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
using Tester;
using Tester.Types;
[Category("Mul"), Ignore("Tested: first half of 2018.")]
[Category("Mul"), Ignore("Tested: second half of 2018.")]
public sealed class CpuTestMul : CpuTest
{
#if Mul

126
Ryujinx.Tests/Cpu/CpuTestSimd.cs
View file

@ -90,7 +90,7 @@ namespace Ryujinx.Tests.Cpu
private const int RndCnt = 1;
[Test, Description("ABS <V><d>, <V><n>")]
public void Abs_S_D([Values(0u)] uint Rd,
public void Abs_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
@ -115,7 +115,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("ABS <Vd>.<T>, <Vn>.<T>")]
public void Abs_V_8B_4H_2S([Values(0u)] uint Rd,
public void Abs_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@ -142,7 +142,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("ABS <Vd>.<T>, <Vn>.<T>")]
public void Abs_V_16B_8H_4S_2D([Values(0u)] uint Rd,
public void Abs_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@ -169,7 +169,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("ADDP <V><d>, <Vn>.<T>")]
public void Addp_S_2DD([Values(0u)] uint Rd,
public void Addp_S_2DD([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
@ -194,7 +194,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("ADDV <V><d>, <Vn>.<T>")]
public void Addv_V_8BB_4HH([Values(0u)] uint Rd,
public void Addv_V_8BB_4HH([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong A,
@ -221,7 +221,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("ADDV <V><d>, <Vn>.<T>")]
public void Addv_V_16BB_8HH_4SS([Values(0u)] uint Rd,
public void Addv_V_16BB_8HH_4SS([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@ -248,7 +248,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CLS <Vd>.<T>, <Vn>.<T>")]
public void Cls_V_8B_4H_2S([Values(0u)] uint Rd,
public void Cls_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@ -275,7 +275,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CLS <Vd>.<T>, <Vn>.<T>")]
public void Cls_V_16B_8H_4S([Values(0u)] uint Rd,
public void Cls_V_16B_8H_4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@ -302,7 +302,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CLZ <Vd>.<T>, <Vn>.<T>")]
public void Clz_V_8B_4H_2S([Values(0u)] uint Rd,
public void Clz_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@ -329,7 +329,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CLZ <Vd>.<T>, <Vn>.<T>")]
public void Clz_V_16B_8H_4S([Values(0u)] uint Rd,
public void Clz_V_16B_8H_4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@ -356,7 +356,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMEQ <V><d>, <V><n>, #0")]
public void Cmeq_S_D([Values(0u)] uint Rd,
public void Cmeq_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
@ -381,7 +381,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMEQ <Vd>.<T>, <Vn>.<T>, #0")]
public void Cmeq_V_8B_4H_2S([Values(0u)] uint Rd,
public void Cmeq_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@ -408,7 +408,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMEQ <Vd>.<T>, <Vn>.<T>, #0")]
public void Cmeq_V_16B_8H_4S_2D([Values(0u)] uint Rd,
public void Cmeq_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@ -435,7 +435,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMGE <V><d>, <V><n>, #0")]
public void Cmge_S_D([Values(0u)] uint Rd,
public void Cmge_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
@ -460,7 +460,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMGE <Vd>.<T>, <Vn>.<T>, #0")]
public void Cmge_V_8B_4H_2S([Values(0u)] uint Rd,
public void Cmge_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@ -487,7 +487,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMGE <Vd>.<T>, <Vn>.<T>, #0")]
public void Cmge_V_16B_8H_4S_2D([Values(0u)] uint Rd,
public void Cmge_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@ -514,7 +514,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMGT <V><d>, <V><n>, #0")]
public void Cmgt_S_D([Values(0u)] uint Rd,
public void Cmgt_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
@ -539,7 +539,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMGT <Vd>.<T>, <Vn>.<T>, #0")]
public void Cmgt_V_8B_4H_2S([Values(0u)] uint Rd,
public void Cmgt_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@ -566,7 +566,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMGT <Vd>.<T>, <Vn>.<T>, #0")]
public void Cmgt_V_16B_8H_4S_2D([Values(0u)] uint Rd,
public void Cmgt_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@ -593,7 +593,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMLE <V><d>, <V><n>, #0")]
public void Cmle_S_D([Values(0u)] uint Rd,
public void Cmle_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
@ -618,7 +618,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMLE <Vd>.<T>, <Vn>.<T>, #0")]
public void Cmle_V_8B_4H_2S([Values(0u)] uint Rd,
public void Cmle_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@ -645,7 +645,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMLE <Vd>.<T>, <Vn>.<T>, #0")]
public void Cmle_V_16B_8H_4S_2D([Values(0u)] uint Rd,
public void Cmle_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@ -672,7 +672,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMLT <V><d>, <V><n>, #0")]
public void Cmlt_S_D([Values(0u)] uint Rd,
public void Cmlt_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
@ -697,7 +697,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMLT <Vd>.<T>, <Vn>.<T>, #0")]
public void Cmlt_V_8B_4H_2S([Values(0u)] uint Rd,
public void Cmlt_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@ -724,7 +724,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CMLT <Vd>.<T>, <Vn>.<T>, #0")]
public void Cmlt_V_16B_8H_4S_2D([Values(0u)] uint Rd,
public void Cmlt_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@ -751,7 +751,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CNT <Vd>.<T>, <Vn>.<T>")]
public void Cnt_V_8B([Values(0u)] uint Rd,
public void Cnt_V_8B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
@ -776,7 +776,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("CNT <Vd>.<T>, <Vn>.<T>")]
public void Cnt_V_16B([Values(0u)] uint Rd,
public void Cnt_V_16B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
@ -801,7 +801,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("NEG <V><d>, <V><n>")]
public void Neg_S_D([Values(0u)] uint Rd,
public void Neg_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A)
@ -826,7 +826,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("NEG <Vd>.<T>, <Vn>.<T>")]
public void Neg_V_8B_4H_2S([Values(0u)] uint Rd,
public void Neg_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@ -853,7 +853,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("NEG <Vd>.<T>, <Vn>.<T>")]
public void Neg_V_16B_8H_4S_2D([Values(0u)] uint Rd,
public void Neg_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@ -880,7 +880,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("NOT <Vd>.<T>, <Vn>.<T>")]
public void Not_V_8B([Values(0u)] uint Rd,
public void Not_V_8B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
@ -905,7 +905,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("NOT <Vd>.<T>, <Vn>.<T>")]
public void Not_V_16B([Values(0u)] uint Rd,
public void Not_V_16B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
@ -930,7 +930,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("RBIT <Vd>.<T>, <Vn>.<T>")]
public void Rbit_V_8B([Values(0u)] uint Rd,
public void Rbit_V_8B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
@ -955,7 +955,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("RBIT <Vd>.<T>, <Vn>.<T>")]
public void Rbit_V_16B([Values(0u)] uint Rd,
public void Rbit_V_16B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
@ -980,7 +980,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("REV16 <Vd>.<T>, <Vn>.<T>")]
public void Rev16_V_8B([Values(0u)] uint Rd,
public void Rev16_V_8B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
@ -1005,7 +1005,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("REV16 <Vd>.<T>, <Vn>.<T>")]
public void Rev16_V_16B([Values(0u)] uint Rd,
public void Rev16_V_16B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong A)
@ -1030,7 +1030,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("REV32 <Vd>.<T>, <Vn>.<T>")]
public void Rev32_V_8B_4H([Values(0u)] uint Rd,
public void Rev32_V_8B_4H([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong A,
@ -1057,7 +1057,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("REV32 <Vd>.<T>, <Vn>.<T>")]
public void Rev32_V_16B_8H([Values(0u)] uint Rd,
public void Rev32_V_16B_8H([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H_")] [Random(RndCnt)] ulong A,
@ -1084,7 +1084,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("REV64 <Vd>.<T>, <Vn>.<T>")]
public void Rev64_V_8B_4H_2S([Values(0u)] uint Rd,
public void Rev64_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@ -1111,7 +1111,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("REV64 <Vd>.<T>, <Vn>.<T>")]
public void Rev64_V_16B_8H_4S([Values(0u)] uint Rd,
public void Rev64_V_16B_8H_4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@ -1138,7 +1138,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQABS <V><d>, <V><n>")]
public void Sqabs_S_B_H_S_D([Values(0u)] uint Rd,
public void Sqabs_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
@ -1169,7 +1169,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQABS <Vd>.<T>, <Vn>.<T>")]
public void Sqabs_V_8B_4H_2S([Values(0u)] uint Rd,
public void Sqabs_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@ -1200,7 +1200,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQABS <Vd>.<T>, <Vn>.<T>")]
public void Sqabs_V_16B_8H_4S_2D([Values(0u)] uint Rd,
public void Sqabs_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@ -1231,7 +1231,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQNEG <V><d>, <V><n>")]
public void Sqneg_S_B_H_S_D([Values(0u)] uint Rd,
public void Sqneg_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
@ -1262,7 +1262,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQNEG <Vd>.<T>, <Vn>.<T>")]
public void Sqneg_V_8B_4H_2S([Values(0u)] uint Rd,
public void Sqneg_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@ -1293,7 +1293,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQNEG <Vd>.<T>, <Vn>.<T>")]
public void Sqneg_V_16B_8H_4S_2D([Values(0u)] uint Rd,
public void Sqneg_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@ -1324,7 +1324,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQXTN <Vb><d>, <Va><n>")]
public void Sqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
public void Sqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A,
@ -1355,7 +1355,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
public void Sqxtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
public void Sqxtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
@ -1386,7 +1386,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
public void Sqxtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
public void Sqxtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
@ -1417,7 +1417,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQXTUN <Vb><d>, <Va><n>")]
public void Sqxtun_S_HB_SH_DS([Values(0u)] uint Rd,
public void Sqxtun_S_HB_SH_DS([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A,
@ -1448,7 +1448,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQXTUN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
public void Sqxtun_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
public void Sqxtun_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
@ -1479,7 +1479,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SQXTUN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
public void Sqxtun_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
public void Sqxtun_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
@ -1510,7 +1510,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SUQADD <V><d>, <V><n>")]
public void Suqadd_S_B_H_S_D([Values(0u)] uint Rd,
public void Suqadd_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
@ -1541,7 +1541,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SUQADD <Vd>.<T>, <Vn>.<T>")]
public void Suqadd_V_8B_4H_2S([Values(0u)] uint Rd,
public void Suqadd_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@ -1572,7 +1572,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("SUQADD <Vd>.<T>, <Vn>.<T>")]
public void Suqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
public void Suqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@ -1603,7 +1603,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("UQXTN <Vb><d>, <Va><n>")]
public void Uqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
public void Uqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A,
@ -1634,7 +1634,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("UQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
public void Uqxtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
public void Uqxtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
@ -1665,7 +1665,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("UQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
public void Uqxtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
public void Uqxtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
@ -1696,7 +1696,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("USQADD <V><d>, <V><n>")]
public void Usqadd_S_B_H_S_D([Values(0u)] uint Rd,
public void Usqadd_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
@ -1727,7 +1727,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("USQADD <Vd>.<T>, <Vn>.<T>")]
public void Usqadd_V_8B_4H_2S([Values(0u)] uint Rd,
public void Usqadd_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
@ -1758,7 +1758,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("USQADD <Vd>.<T>, <Vn>.<T>")]
public void Usqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
public void Usqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
@ -1789,7 +1789,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("XTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
public void Xtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
public void Xtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
@ -1816,7 +1816,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Description("XTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
public void Xtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
public void Xtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,

421
Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
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File diff suppressed because it is too large Load diff

204
Ryujinx.Tests/Cpu/Tester/Instructions.cs
View file

@ -5075,6 +5075,210 @@ namespace Ryujinx.Tests.Cpu.Tester
V(d, result);
}
// sqdmulh_advsimd_vec.html#SQDMULH_asisdsame_only
public static void Sqdmulh_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = false;
/* Decode Scalar */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' || size == '00' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = esize;
int elements = 1;
bool rounding = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand1 = V(datasize, n);
Bits operand2 = V(datasize, m);
BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0);
BigInteger element1;
BigInteger element2;
BigInteger product;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
element1 = SInt(Elem(operand1, e, esize));
element2 = SInt(Elem(operand2, e, esize));
product = (2 * element1 * element2) + round_const;
(Bits _result, bool _sat) = SignedSatQ(product >> esize, esize);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// sqdmulh_advsimd_vec.html#SQDMULH_asimdsame_only
public static void Sqdmulh_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = false;
/* Decode Vector */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' || size == '00' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = (Q ? 128 : 64);
int elements = datasize / esize;
bool rounding = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand1 = V(datasize, n);
Bits operand2 = V(datasize, m);
BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0);
BigInteger element1;
BigInteger element2;
BigInteger product;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
element1 = SInt(Elem(operand1, e, esize));
element2 = SInt(Elem(operand2, e, esize));
product = (2 * element1 * element2) + round_const;
(Bits _result, bool _sat) = SignedSatQ(product >> esize, esize);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// sqrdmulh_advsimd_vec.html#SQRDMULH_asisdsame_only
public static void Sqrdmulh_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = true;
/* Decode Scalar */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' || size == '00' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = esize;
int elements = 1;
bool rounding = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand1 = V(datasize, n);
Bits operand2 = V(datasize, m);
BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0);
BigInteger element1;
BigInteger element2;
BigInteger product;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
element1 = SInt(Elem(operand1, e, esize));
element2 = SInt(Elem(operand2, e, esize));
product = (2 * element1 * element2) + round_const;
(Bits _result, bool _sat) = SignedSatQ(product >> esize, esize);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// sqrdmulh_advsimd_vec.html#SQRDMULH_asimdsame_only
public static void Sqrdmulh_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = true;
/* Decode Vector */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' || size == '00' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = (Q ? 128 : 64);
int elements = datasize / esize;
bool rounding = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand1 = V(datasize, n);
Bits operand2 = V(datasize, m);
BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0);
BigInteger element1;
BigInteger element2;
BigInteger product;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
element1 = SInt(Elem(operand1, e, esize));
element2 = SInt(Elem(operand2, e, esize));
product = (2 * element1 * element2) + round_const;
(Bits _result, bool _sat) = SignedSatQ(product >> esize, esize);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// sqsub_advsimd.html#SQSUB_asisdsame_only
public static void Sqsub_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
{

9
Ryujinx.Tests/Ryujinx.Tests.csproj
View file

@ -1,20 +1,25 @@
<Project Sdk="Microsoft.NET.Sdk">
<Project Sdk="Microsoft.NET.Sdk">
<PropertyGroup>
<TargetFramework>netcoreapp2.1</TargetFramework>
<RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
<OutputType>Exe</OutputType>
<IsPackable>false</IsPackable>
</PropertyGroup>
<PropertyGroup>
<GenerateAssemblyInfo>false</GenerateAssemblyInfo>
</PropertyGroup>
<ItemGroup>
<PackageReference Include="Microsoft.NET.Test.Sdk" Version="15.7.0" />
<PackageReference Include="Microsoft.NET.Test.Sdk" Version="15.8.0" />
<PackageReference Include="NUnit" Version="3.10.1" />
<PackageReference Include="NUnit3TestAdapter" Version="3.10.0" />
<PackageReference Include="System.Runtime.Intrinsics.Experimental" Version="4.5.0-rc1" />
</ItemGroup>
<ItemGroup>
<ProjectReference Include="..\ChocolArm64\ChocolArm64.csproj" />
</ItemGroup>
</Project>