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Add BIC/ORR Vd.T, #imm fast path (#2279)

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* Add fast path for BIC Vd.T, #imm

* Add fast path for ORR Vd.T, #imm

* Set PTC version

* Fixup Exception to InvalidOperationException
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FICTURE7 2021-05-20 16:09:17 +04:00 • committed by GitHub
parent 49745cfa37
commit 0181068016
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3 changed files with 65 additions and 5 deletions
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59
ARMeilleure/Instructions/InstEmitSimdLogical.cs
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@ -1,6 +1,7 @@
using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using System;
using System.Diagnostics;
using static ARMeilleure.Instructions.InstEmitHelper;
@ -64,10 +65,35 @@ namespace ARMeilleure.Instructions
public static void Bic_Vi(ArmEmitterContext context)
{
EmitVectorImmBinaryOp(context, (op1, op2) =>
if (Optimizations.UseSse2)
{
return context.BitwiseAnd(op1, context.BitwiseNot(op2));
});
OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
int eSize = 8 << op.Size;
Operand d = GetVec(op.Rd);
Operand imm = eSize switch {
16 => X86GetAllElements(context, (short)~op.Immediate),
32 => X86GetAllElements(context, (int)~op.Immediate),
_ => throw new InvalidOperationException($"Invalid element size {eSize}.")
};
Operand res = context.AddIntrinsic(Intrinsic.X86Pand, d, imm);
if (op.RegisterSize == RegisterSize.Simd64)
{
res = context.VectorZeroUpper64(res);
}
context.Copy(GetVec(op.Rd), res);
}
else
{
EmitVectorImmBinaryOp(context, (op1, op2) =>
{
return context.BitwiseAnd(op1, context.BitwiseNot(op2));
});
}
}
public static void Bif_V(ArmEmitterContext context)
@ -278,7 +304,32 @@ namespace ARMeilleure.Instructions
public static void Orr_Vi(ArmEmitterContext context)
{
EmitVectorImmBinaryOp(context, (op1, op2) => context.BitwiseOr(op1, op2));
if (Optimizations.UseSse2)
{
OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
int eSize = 8 << op.Size;
Operand d = GetVec(op.Rd);
Operand imm = eSize switch {
16 => X86GetAllElements(context, (short)op.Immediate),
32 => X86GetAllElements(context, (int)op.Immediate),
_ => throw new InvalidOperationException($"Invalid element size {eSize}.")
};
Operand res = context.AddIntrinsic(Intrinsic.X86Por, d, imm);
if (op.RegisterSize == RegisterSize.Simd64)
{
res = context.VectorZeroUpper64(res);
}
context.Copy(GetVec(op.Rd), res);
}
else
{
EmitVectorImmBinaryOp(context, (op1, op2) => context.BitwiseOr(op1, op2));
}
}
public static void Rbit_V(ArmEmitterContext context)