[Controller] Added board config for custom controller STeMCell (#16287)
Co-authored-by: Mariappan Ramasamy <947300+Mariappan@users.noreply.github.com> Co-authored-by: Mariappan Ramasamy <maari@basis-ai.com> Co-authored-by: Sadek Baroudi <sadekbaroudi@gmail.com>
This commit is contained in:
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commit
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11 changed files with 411 additions and 1 deletions
15
platforms/chibios/boards/STEMCELL/board/board.mk
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15
platforms/chibios/boards/STEMCELL/board/board.mk
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# Copyright 2022 Mega Mind (@megamind4089)
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Default pin config of nucleo64_411re has most pins in input pull up mode
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# List of all the board related files.
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BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE/board.c
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# Required include directories
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BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE
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# Shared variables
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ALLCSRC += $(BOARDSRC)
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ALLINC += $(BOARDINC)
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8
platforms/chibios/boards/STEMCELL/configs/board.h
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platforms/chibios/boards/STEMCELL/configs/board.h
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// Copyright 2022 Mega Mind (@megamind4089)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include_next "board.h"
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#undef STM32_HSE_BYPASS
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9
platforms/chibios/boards/STEMCELL/configs/chconf.h
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platforms/chibios/boards/STEMCELL/configs/chconf.h
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// Copyright 2022 Mega Mind (@megamind4089)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#define CH_CFG_ST_RESOLUTION 16
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#define CH_CFG_ST_FREQUENCY 10000
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#include_next <chconf.h>
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29
platforms/chibios/boards/STEMCELL/configs/config.h
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platforms/chibios/boards/STEMCELL/configs/config.h
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// Copyright 2022 Mega Mind(@megamind4089)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
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# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
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#endif
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/**======================
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** I2C Driver
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*========================**/
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#if !defined(I2C1_SDA_PIN)
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# define I2C1_SDA_PIN D0
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#endif
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#if !defined(I2C1_SCL_PIN)
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# define I2C1_SCL_PIN D1
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#endif
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/**======================
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** SERIAL Driver
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*========================**/
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#if !defined(SERIAL_USART_DRIVER)
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# define SERIAL_USART_DRIVER SD2
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#endif
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11
platforms/chibios/boards/STEMCELL/configs/halconf.h
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platforms/chibios/boards/STEMCELL/configs/halconf.h
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// Copyright 2022 Mega Mind (@megamind4089)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#define PAL_USE_WAIT TRUE
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#define PAL_USE_CALLBACKS TRUE
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#define HAL_USE_I2C TRUE
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#define HAL_USE_SERIAL TRUE
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#include_next <halconf.h>
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231
platforms/chibios/boards/STEMCELL/configs/mcuconf.h
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platforms/chibios/boards/STEMCELL/configs/mcuconf.h
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// Copyright 2022 Mega Mind (@megamind4089)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#ifndef MCUCONF_H
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#define MCUCONF_H
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/*
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* STM32F4xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 15...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#define STM32F4xx_MCUCONF
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#define STM32F411_MCUCONF
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/*
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* HAL driver system settings.
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_BKPRAM_ENABLE FALSE
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#define STM32_HSI_ENABLED TRUE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_HSE_ENABLED TRUE
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#define STM32_LSE_ENABLED FALSE
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#define STM32_CLOCK48_REQUIRED TRUE
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_PLLM_VALUE 8
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#define STM32_PLLN_VALUE 336
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#define STM32_PLLP_VALUE 4
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#define STM32_PLLQ_VALUE 7
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#define STM32_PPRE2 STM32_PPRE2_DIV1
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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#define STM32_RTCPRE_VALUE 8
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#define STM32_MCO1SEL STM32_MCO1SEL_HSI
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#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
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#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
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#define STM32_I2SSRC STM32_I2SSRC_CKIN
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SR_VALUE 5
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/*
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* IRQ system settings.
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*/
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#define STM32_IRQ_EXTI0_PRIORITY 6
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#define STM32_IRQ_EXTI1_PRIORITY 6
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#define STM32_IRQ_EXTI2_PRIORITY 6
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#define STM32_IRQ_EXTI3_PRIORITY 6
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#define STM32_IRQ_EXTI4_PRIORITY 6
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#define STM32_IRQ_EXTI5_9_PRIORITY 6
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#define STM32_IRQ_EXTI10_15_PRIORITY 6
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#define STM32_IRQ_EXTI16_PRIORITY 6
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#define STM32_IRQ_EXTI17_PRIORITY 15
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#define STM32_IRQ_EXTI18_PRIORITY 6
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#define STM32_IRQ_EXTI19_PRIORITY 6
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#define STM32_IRQ_EXTI20_PRIORITY 6
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#define STM32_IRQ_EXTI21_PRIORITY 15
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#define STM32_IRQ_EXTI22_PRIORITY 15
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#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
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#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
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#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
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#define STM32_IRQ_TIM1_CC_PRIORITY 7
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#define STM32_IRQ_TIM2_PRIORITY 7
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#define STM32_IRQ_TIM3_PRIORITY 7
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#define STM32_IRQ_TIM4_PRIORITY 7
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#define STM32_IRQ_TIM5_PRIORITY 7
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#define STM32_IRQ_USART1_PRIORITY 12
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#define STM32_IRQ_USART2_PRIORITY 12
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#define STM32_IRQ_USART6_PRIORITY 12
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/*
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* ADC driver system settings.
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*/
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#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_IRQ_PRIORITY 6
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
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/*
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* GPT driver system settings.
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*/
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#define STM32_GPT_USE_TIM1 FALSE
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#define STM32_GPT_USE_TIM2 FALSE
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#define STM32_GPT_USE_TIM3 FALSE
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#define STM32_GPT_USE_TIM4 FALSE
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#define STM32_GPT_USE_TIM5 FALSE
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#define STM32_GPT_USE_TIM9 FALSE
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#define STM32_GPT_USE_TIM10 FALSE
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#define STM32_GPT_USE_TIM11 FALSE
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/*
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* I2C driver system settings.
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*/
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#define STM32_I2C_USE_I2C1 TRUE
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#define STM32_I2C_USE_I2C2 FALSE
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#define STM32_I2C_USE_I2C3 FALSE
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#define STM32_I2C_BUSY_TIMEOUT 50
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_I2C_I2C1_IRQ_PRIORITY 5
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#define STM32_I2C_I2C2_IRQ_PRIORITY 5
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#define STM32_I2C_I2C3_IRQ_PRIORITY 5
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#define STM32_I2C_I2C1_DMA_PRIORITY 3
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#define STM32_I2C_I2C2_DMA_PRIORITY 3
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#define STM32_I2C_I2C3_DMA_PRIORITY 3
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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* I2S driver system settings.
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*/
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#define STM32_I2S_USE_SPI2 FALSE
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#define STM32_I2S_USE_SPI3 FALSE
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#define STM32_I2S_SPI2_IRQ_PRIORITY 10
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#define STM32_I2S_SPI3_IRQ_PRIORITY 10
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#define STM32_I2S_SPI2_DMA_PRIORITY 1
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#define STM32_I2S_SPI3_DMA_PRIORITY 1
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#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
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/*
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* ICU driver system settings.
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*/
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#define STM32_ICU_USE_TIM1 FALSE
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#define STM32_ICU_USE_TIM2 FALSE
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#define STM32_ICU_USE_TIM3 FALSE
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#define STM32_ICU_USE_TIM4 FALSE
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#define STM32_ICU_USE_TIM5 FALSE
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#define STM32_ICU_USE_TIM9 FALSE
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#define STM32_ICU_USE_TIM10 FALSE
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#define STM32_ICU_USE_TIM11 FALSE
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/*
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* PWM driver system settings.
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*/
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#define STM32_PWM_USE_TIM1 FALSE
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#define STM32_PWM_USE_TIM2 FALSE
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#define STM32_PWM_USE_TIM3 FALSE
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#define STM32_PWM_USE_TIM4 FALSE
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#define STM32_PWM_USE_TIM5 FALSE
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#define STM32_PWM_USE_TIM9 FALSE
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#define STM32_PWM_USE_TIM10 FALSE
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#define STM32_PWM_USE_TIM11 FALSE
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/*
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* SERIAL driver system settings.
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*/
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#define STM32_SERIAL_USE_USART1 TRUE
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#define STM32_SERIAL_USE_USART2 TRUE
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#define STM32_SERIAL_USE_USART6 FALSE
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/*
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* SPI driver system settings.
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*/
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#define STM32_SPI_USE_SPI1 FALSE
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#define STM32_SPI_USE_SPI2 FALSE
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#define STM32_SPI_USE_SPI3 FALSE
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI3_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10
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#define STM32_SPI_SPI2_IRQ_PRIORITY 10
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#define STM32_SPI_SPI3_IRQ_PRIORITY 10
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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/*
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* ST driver system settings.
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*/
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#define STM32_ST_IRQ_PRIORITY 8
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#define STM32_ST_USE_TIMER 2
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/*
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* UART driver system settings.
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*/
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USE_USART6 FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART6_DMA_PRIORITY 0
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#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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/*
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* USB driver system settings.
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*/
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#define STM32_USB_USE_OTG1 TRUE
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#define STM32_USB_OTG1_IRQ_PRIORITY 14
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#define STM32_USB_OTG1_RX_FIFO_SIZE 512
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#define STM32_USB_HOST_WAKEUP_DURATION 2
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/*
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* WDG driver system settings.
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*/
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#define STM32_WDG_USE_IWDG FALSE
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#endif /* MCUCONF_H */
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// Copyright 2022 Mega Mind (@megamind4089)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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// Pindefs for v2.0.0
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// https://megamind4089.github.io/STeMCell/pinout/
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// Left side (front)
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#ifdef STEMCELL_UART_SWAP
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# define D3 PAL_LINE(GPIOA, 3)
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# define D2 PAL_LINE(GPIOA, 2)
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#else
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# define D3 PAL_LINE(GPIOA, 2)
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# define D2 PAL_LINE(GPIOA, 3)
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#endif
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// GND
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// GND
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#ifdef STEMCELL_I2C_SWAP
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# define D1 PAL_LINE(GPIOB, 6)
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# define D0 PAL_LINE(GPIOB, 7)
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#else
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# define D1 PAL_LINE(GPIOB, 7)
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# define D0 PAL_LINE(GPIOB, 6)
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#endif
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#define D4 PAL_LINE(GPIOA, 15)
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#define C6 PAL_LINE(GPIOB, 3)
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#define D7 PAL_LINE(GPIOB, 4)
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#define E6 PAL_LINE(GPIOB, 5)
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#define B4 PAL_LINE(GPIOB, 8)
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#define B5 PAL_LINE(GPIOB, 9)
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// Right side (front)
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// RAW
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// GND
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// RESET
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// VCC
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#define F4 PAL_LINE(GPIOB, 10)
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#define F5 PAL_LINE(GPIOB, 2)
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#define F6 PAL_LINE(GPIOB, 1)
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#define F7 PAL_LINE(GPIOB, 0)
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#define B1 PAL_LINE(GPIOA, 5)
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#define B3 PAL_LINE(GPIOA, 6)
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#define B2 PAL_LINE(GPIOA, 7)
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#define B6 PAL_LINE(GPIOA, 4)
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// Extra elite-c compatible pinout
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#define B7 PAL_LINE(GPIOC, 13)
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#define D5 PAL_LINE(GPIOC, 14)
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#define C7 PAL_LINE(GPIOC, 15)
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#define F1 PAL_LINE(GPIOA, 0)
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#define F0 PAL_LINE(GPIOA, 1)
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// TX/RX pins of promicro
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#define B0 PAL_LINE(GPIOA, 9) // unconnected pin
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# Copyright 2022 Mega Mind (@megamind4089)
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# SPDX-License-Identifier: GPL-2.0-or-later
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MCU := STM32F411
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BOARD := STEMCELL
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BOOTLOADER := tinyuf2
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SERIAL_DRIVER ?= usart
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WS2812_DRIVER ?= bitbang
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EEPROM_DRIVER = wear_leveling
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WEAR_LEVELING_DRIVER = legacy
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ifeq ($(strip $(STMC_US)), yes)
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OPT_DEFS += -DSTEMCELL_UART_SWAP
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endif
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ifeq ($(strip $(STMC_IS)), yes)
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OPT_DEFS += -DSTEMCELL_I2C_SWAP
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endif
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