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dc0e46e Rename LUFA to LUFA-git
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git-subtree-dir: tmk_core
git-subtree-split: dc0e46eaa4367d4e218f8816e3c117895820f07c
This commit is contained in:
tmk 2015-05-13 11:13:10 +09:00
parent 4d116a04e9
commit f6d56675f9
1575 changed files with 421901 additions and 63190 deletions
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80
protocol/lufa/LUFA-git/LUFA/Platform/Platform.h Normal file
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/*
LUFA Library
Copyright (C) Dean Camera, 2014.
dean [at] fourwalledcubicle [dot] com
www.lufa-lib.org
*/
/*
Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com)
Permission to use, copy, modify, distribute, and sell this
software and its documentation for any purpose is hereby granted
without fee, provided that the above copyright notice appear in
all copies and that both that the copyright notice and this
permission notice and warranty disclaimer appear in supporting
documentation, and that the name of the author not be used in
advertising or publicity pertaining to distribution of the
software without specific, written prior permission.
The author disclaims all warranties with regard to this
software, including all implied warranties of merchantability
and fitness. In no event shall the author be liable for any
special, indirect or consequential damages or any damages
whatsoever resulting from loss of use, data or profits, whether
in an action of contract, negligence or other tortious action,
arising out of or in connection with the use or performance of
this software.
*/
/** \file
* \brief Architecture Specific Hardware Platform Drivers.
*
* This file is the master dispatch header file for the device-specific hardware platform drivers, for low level
* hardware configuration and management. The platform drivers are a set of drivers which are designed to provide
* a high level management layer for the various low level system functions such as clock control and interrupt
* management.
*
* User code may choose to either include this master dispatch header file to include all available platform
* driver header files for the current architecture, or may choose to only include the specific platform driver
* modules required for a particular application.
*/
/** \defgroup Group_PlatformDrivers System Platform Drivers - LUFA/Platform/Platform.h
* \brief Hardware platform drivers.
*
* \section Sec_PlatformDrivers_Dependencies Module Source Dependencies
* The following files must be built with any user project that uses this module:
* - <b>UC3 Architecture Only:</b> LUFA/Platform/UC3/InterruptManagement.c <i>(Makefile source module name: LUFA_SRC_PLATFORM)</i>
* - <b>UC3 Architecture Only:</b> LUFA/Platform/UC3/Exception.S <i>(Makefile source module name: LUFA_SRC_PLATFORM)</i>
*
* \section Sec_PlatformDrivers_ModDescription Module Description
* Device-specific hardware platform drivers, for low level hardware configuration and management. The platform
* drivers are a set of drivers which are designed to provide a high level management layer for the various low level
* system functions such as clock control and interrupt management.
*
* User code may choose to either include this master dispatch header file to include all available platform
* driver header files for the current architecture, or may choose to only include the specific platform driver
* modules required for a particular application.
*
* \note The exact APIs and availability of sub-modules within the platform driver group may vary depending on the
* target used - see individual target module documentation for the API specific to your target processor.
*/
#ifndef __LUFA_PLATFORM_H__
#define __LUFA_PLATFORM_H__
/* Includes: */
#include "../Common/Common.h"
/* Includes: */
#if (ARCH == ARCH_UC3)
#include "UC3/ClockManagement.h"
#include "UC3/InterruptManagement.h"
#elif (ARCH == ARCH_XMEGA)
#include "XMEGA/ClockManagement.h"
#endif
#endif

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protocol/lufa/LUFA-git/LUFA/Platform/UC3/ClockManagement.h Normal file
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/*
LUFA Library
Copyright (C) Dean Camera, 2014.
dean [at] fourwalledcubicle [dot] com
www.lufa-lib.org
*/
/*
Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com)
Permission to use, copy, modify, distribute, and sell this
software and its documentation for any purpose is hereby granted
without fee, provided that the above copyright notice appear in
all copies and that both that the copyright notice and this
permission notice and warranty disclaimer appear in supporting
documentation, and that the name of the author not be used in
advertising or publicity pertaining to distribution of the
software without specific, written prior permission.
The author disclaims all warranties with regard to this
software, including all implied warranties of merchantability
and fitness. In no event shall the author be liable for any
special, indirect or consequential damages or any damages
whatsoever resulting from loss of use, data or profits, whether
in an action of contract, negligence or other tortious action,
arising out of or in connection with the use or performance of
this software.
*/
/** \file
* \brief Module Clock Driver for the AVR32 UC3 microcontrollers.
*
* Clock management driver for the AVR32 UC3 microcontrollers. This driver allows for the configuration
* of the various clocks within the device to clock the various peripherals.
*/
/** \ingroup Group_PlatformDrivers_UC3
* \defgroup Group_PlatformDrivers_UC3Clocks Clock Management Driver - LUFA/Platform/UC3/ClockManagement.h
* \brief Module Clock Driver for the AVR32 UC3 microcontrollers.
*
* \section Sec_PlatformDrivers_UC3Clocks_Dependencies Module Source Dependencies
* The following files must be built with any user project that uses this module:
* - None
*
* \section Sec_PlatformDrivers_UC3Clocks_ModDescription Module Description
* Clock management driver for the AVR32 UC3 microcontrollers. This driver allows for the configuration
* of the various clocks within the device to clock the various peripherals.
*
* Usage Example:
* \code
* #include <LUFA/Platform/UC3/ClockManagement.h>
*
* void main(void)
* {
* // Start the master external oscillator which will be used as the main clock reference
* UC3CLK_StartExternalOscillator(0, EXOSC_MODE_8MHZ_OR_MORE, EXOSC_START_0CLK);
*
* // Start the PLL for the CPU clock, switch CPU to it
* UC3CLK_StartPLL(0, CLOCK_SRC_OSC0, 12000000, F_CPU);
* UC3CLK_SetCPUClockSource(CLOCK_SRC_PLL0, F_CPU);
*
* // Start the PLL for the USB Generic Clock module
* UC3CLK_StartPLL(1, CLOCK_SRC_OSC0, 12000000, 48000000);
* }
* \endcode
*
* @{
*/
#ifndef _UC3_CLOCK_MANAGEMENT_H_
#define _UC3_CLOCK_MANAGEMENT_H_
/* Includes: */
#include "../../Common/Common.h"
/* Enable C linkage for C++ Compilers: */
#if defined(__cplusplus)
extern "C" {
#endif
/* Public Interface - May be used in end-application: */
/* Macros: */
/** Enum for the possible external oscillator types. */
enum UC3_Extern_OSC_ClockTypes_t
{
EXOSC_MODE_CLOCK = AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK, /**< External clock (non-crystal) mode. */
EXOSC_MODE_900KHZ_MAX = AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G0, /**< External crystal oscillator equal to or slower than 900KHz. */
EXOSC_MODE_3MHZ_MAX = AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G1, /**< External crystal oscillator equal to or slower than 3MHz. */
EXOSC_MODE_8MHZ_MAX = AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2, /**< External crystal oscillator equal to or slower than 8MHz. */
EXOSC_MODE_8MHZ_OR_MORE = AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3, /**< External crystal oscillator equal to or faster than 8MHz. */
};
/** Enum for the possible external oscillator startup times. */
enum UC3_Extern_OSC_ClockStartup_t
{
EXOSC_START_0CLK = AVR32_PM_OSCCTRL0_STARTUP_0_RCOSC, /**< Immediate startup, no delay. */
EXOSC_START_64CLK = AVR32_PM_OSCCTRL0_STARTUP_64_RCOSC, /**< Wait 64 clock cycles before startup for stability. */
EXOSC_START_128CLK = AVR32_PM_OSCCTRL0_STARTUP_128_RCOSC, /**< Wait 128 clock cycles before startup for stability. */
EXOSC_START_2048CLK = AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC, /**< Wait 2048 clock cycles before startup for stability. */
EXOSC_START_4096CLK = AVR32_PM_OSCCTRL0_STARTUP_4096_RCOSC, /**< Wait 4096 clock cycles before startup for stability. */
EXOSC_START_8192CLK = AVR32_PM_OSCCTRL0_STARTUP_8192_RCOSC, /**< Wait 8192 clock cycles before startup for stability. */
EXOSC_START_16384CLK = AVR32_PM_OSCCTRL0_STARTUP_16384_RCOSC, /**< Wait 16384 clock cycles before startup for stability. */
};
/** Enum for the possible module clock sources. */
enum UC3_System_ClockSource_t
{
CLOCK_SRC_SLOW_CLK = 0, /**< Clock sourced from the internal slow clock. */
CLOCK_SRC_OSC0 = 1, /**< Clock sourced from the Oscillator 0 clock. */
CLOCK_SRC_OSC1 = 2, /**< Clock sourced from the Oscillator 1 clock. */
CLOCK_SRC_PLL0 = 3, /**< Clock sourced from the PLL 0 clock. */
CLOCK_SRC_PLL1 = 4, /**< Clock sourced from the PLL 1 clock. */
};
/* Inline Functions: */
/** Starts the given external oscillator of the UC3 microcontroller, with the given options. This routine blocks until
* the oscillator is ready for use.
*
* \param[in] Channel Index of the external oscillator to start.
* \param[in] Type Type of clock attached to the given oscillator channel, a value from \ref UC3_Extern_OSC_ClockTypes_t.
* \param[in] Startup Startup time of the external oscillator, a value from \ref UC3_Extern_OSC_ClockStartup_t.
*
* \return Boolean \c true if the external oscillator was successfully started, \c false if invalid parameters specified.
*/
static inline bool UC3CLK_StartExternalOscillator(const uint8_t Channel,
const uint8_t Type,
const uint8_t Startup) ATTR_ALWAYS_INLINE;
static inline bool UC3CLK_StartExternalOscillator(const uint8_t Channel,
const uint8_t Type,
const uint8_t Startup)
{
switch (Channel)
{
case 0:
AVR32_PM.OSCCTRL0.startup = Startup;
AVR32_PM.OSCCTRL0.mode = Type;
break;
case 1:
AVR32_PM.OSCCTRL1.startup = Startup;
AVR32_PM.OSCCTRL1.mode = Type;
break;
default:
return false;
}
AVR32_PM.mcctrl |= (1 << (AVR32_PM_MCCTRL_OSC0EN_OFFSET + Channel));
while (!(AVR32_PM.poscsr & (1 << (AVR32_PM_POSCSR_OSC0RDY_OFFSET + Channel))));
return true;
}
/** Stops the given external oscillator of the UC3 microcontroller.
*
* \param[in] Channel Index of the external oscillator to stop.
*/
static inline void UC3CLK_StopExternalOscillator(const uint8_t Channel) ATTR_ALWAYS_INLINE;
static inline void UC3CLK_StopExternalOscillator(const uint8_t Channel)
{
AVR32_PM.mcctrl &= ~(1 << (AVR32_PM_MCCTRL_OSC0EN_OFFSET + Channel));
}
/** Starts the given PLL of the UC3 microcontroller, with the given options. This routine blocks until the PLL is ready for use.
*
* \attention The output frequency must be equal to or greater than the source frequency.
*
* \param[in] Channel Index of the PLL to start.
* \param[in] Source Clock source for the PLL, a value from \ref UC3_System_ClockSource_t.
* \param[in] SourceFreq Frequency of the PLL's clock source, in Hz.
* \param[in] Frequency Target frequency of the PLL's output.
*
* \return Boolean \c true if the PLL was successfully started, \c false if invalid parameters specified.
*/
static inline bool UC3CLK_StartPLL(const uint8_t Channel,
const uint8_t Source,
const uint32_t SourceFreq,
const uint32_t Frequency) ATTR_ALWAYS_INLINE;
static inline bool UC3CLK_StartPLL(const uint8_t Channel,
const uint8_t Source,
const uint32_t SourceFreq,
const uint32_t Frequency)
{
if (SourceFreq > Frequency)
return false;
switch (Source)
{
case CLOCK_SRC_OSC0:
AVR32_PM.PLL[Channel].pllosc = 0;
break;
case CLOCK_SRC_OSC1:
AVR32_PM.PLL[Channel].pllosc = 1;
break;
default:
return false;
}
AVR32_PM.PLL[Channel].pllmul = (Frequency / SourceFreq) ? (((Frequency / SourceFreq) - 1) / 2) : 0;
AVR32_PM.PLL[Channel].plldiv = 0;
AVR32_PM.PLL[Channel].pllen = true;
while (!(AVR32_PM.poscsr & (1 << (AVR32_PM_POSCSR_LOCK0_OFFSET + Channel))));
return true;
}
/** Stops the given PLL of the UC3 microcontroller.
*
* \param[in] Channel Index of the PLL to stop.
*/
static inline void UC3CLK_StopPLL(const uint8_t Channel) ATTR_ALWAYS_INLINE;
static inline void UC3CLK_StopPLL(const uint8_t Channel)
{
AVR32_PM.PLL[Channel].pllen = false;
}
/** Starts the given Generic Clock of the UC3 microcontroller, with the given options.
*
* \param[in] Channel Index of the Generic Clock to start.
* \param[in] Source Clock source for the Generic Clock, a value from \ref UC3_System_ClockSource_t.
* \param[in] SourceFreq Frequency of the Generic Clock's clock source, in Hz.
* \param[in] Frequency Target frequency of the Generic Clock's output.
*
* \return Boolean \c true if the Generic Clock was successfully started, \c false if invalid parameters specified.
*/
static inline bool UC3CLK_StartGenericClock(const uint8_t Channel,
const uint8_t Source,
const uint32_t SourceFreq,
const uint32_t Frequency) ATTR_ALWAYS_INLINE;
static inline bool UC3CLK_StartGenericClock(const uint8_t Channel,
const uint8_t Source,
const uint32_t SourceFreq,
const uint32_t Frequency)
{
if (Channel >= AVR32_PM_GCLK_NUM)
return false;
if (SourceFreq < Frequency)
return false;
switch (Source)
{
case CLOCK_SRC_OSC0:
AVR32_PM.GCCTRL[Channel].pllsel = false;
AVR32_PM.GCCTRL[Channel].oscsel = 0;
break;
case CLOCK_SRC_OSC1:
AVR32_PM.GCCTRL[Channel].pllsel = false;
AVR32_PM.GCCTRL[Channel].oscsel = 1;
break;
case CLOCK_SRC_PLL0:
AVR32_PM.GCCTRL[Channel].pllsel = true;
AVR32_PM.GCCTRL[Channel].oscsel = 0;
break;
case CLOCK_SRC_PLL1:
AVR32_PM.GCCTRL[Channel].pllsel = true;
AVR32_PM.GCCTRL[Channel].oscsel = 1;
break;
default:
return false;
}
AVR32_PM.GCCTRL[Channel].diven = (SourceFreq > Frequency) ? true : false;
AVR32_PM.GCCTRL[Channel].div = (((SourceFreq / Frequency) - 1) / 2);
AVR32_PM.GCCTRL[Channel].cen = true;
return true;
}
/** Stops the given generic clock of the UC3 microcontroller.
*
* \param[in] Channel Index of the generic clock to stop.
*
* \return Boolean \c true if the generic clock was successfully stopped, \c false if invalid parameters specified.
*/
static inline bool UC3CLK_StopGenericClock(const uint8_t Channel) ATTR_ALWAYS_INLINE;
static inline bool UC3CLK_StopGenericClock(const uint8_t Channel)
{
if (Channel >= AVR32_PM_GCLK_NUM)
return false;
AVR32_PM.GCCTRL[Channel].cen = false;
return true;
}
/** Sets the clock source for the main microcontroller core. The given clock source should be configured
* and ready for use before this function is called.
*
* This function will configure the FLASH controller's wait states automatically to suit the given clock source.
*
* \param[in] Source Clock source for the CPU core, a value from \ref UC3_System_ClockSource_t.
* \param[in] SourceFreq Frequency of the CPU core's clock source, in Hz.
*
* \return Boolean \c true if the CPU core clock was successfully altered, \c false if invalid parameters specified.
*/
static inline bool UC3CLK_SetCPUClockSource(const uint8_t Source,
const uint32_t SourceFreq) ATTR_ALWAYS_INLINE;
static inline bool UC3CLK_SetCPUClockSource(const uint8_t Source,
const uint32_t SourceFreq)
{
if (SourceFreq > AVR32_PM_CPU_MAX_FREQ)
return false;
AVR32_FLASHC.FCR.fws = (SourceFreq > AVR32_FLASHC_FWS_0_MAX_FREQ) ? true : false;
switch (Source)
{
#if defined(AVR32_PM_MCCTRL_MCSEL_SLOW)
case CLOCK_SRC_SLOW_CLK:
AVR32_PM.MCCTRL.mcsel = AVR32_PM_MCCTRL_MCSEL_SLOW;
break;
#endif
#if defined(AVR32_PM_MCCTRL_MCSEL_OSC0)
case CLOCK_SRC_OSC0:
AVR32_PM.MCCTRL.mcsel = AVR32_PM_MCCTRL_MCSEL_OSC0;
break;
#endif
#if defined(AVR32_PM_MCCTRL_MCSEL_PLL0)
case CLOCK_SRC_PLL0:
AVR32_PM.MCCTRL.mcsel = AVR32_PM_MCCTRL_MCSEL_PLL0;
break;
#endif
default:
return false;
}
return true;
}
/* Disable C linkage for C++ Compilers: */
#if defined(__cplusplus)
}
#endif
#endif
/** @} */

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protocol/lufa/LUFA-git/LUFA/Platform/UC3/Exception.S Normal file
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/*
LUFA Library
Copyright (C) Dean Camera, 2014.
dean [at] fourwalledcubicle [dot] com
www.lufa-lib.org
*/
/*
Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com)
Permission to use, copy, modify, distribute, and sell this
software and its documentation for any purpose is hereby granted
without fee, provided that the above copyright notice appear in
all copies and that both that the copyright notice and this
permission notice and warranty disclaimer appear in supporting
documentation, and that the name of the author not be used in
advertising or publicity pertaining to distribution of the
software without specific, written prior permission.
The author disclaims all warranties with regard to this
software, including all implied warranties of merchantability
and fitness. In no event shall the author be liable for any
special, indirect or consequential damages or any damages
whatsoever resulting from loss of use, data or profits, whether
in an action of contract, negligence or other tortious action,
arising out of or in connection with the use or performance of
this software.
*/
#if defined(__AVR32__)
#include <avr32/io.h>
.section .exception_handlers, "ax", @progbits
// ================= EXCEPTION TABLE ================
.balign 0x200
.global EVBA_Table
EVBA_Table:
.org 0x000
Exception_Unrecoverable_Exception:
rjmp $
.org 0x004
Exception_TLB_Multiple_Hit:
rjmp $
.org 0x008
Exception_Bus_Error_Data_Fetch:
rjmp $
.org 0x00C
Exception_Bus_Error_Instruction_Fetch:
rjmp $
.org 0x010
Exception_NMI:
rjmp $
.org 0x014
Exception_Instruction_Address:
rjmp $
.org 0x018
Exception_ITLB_Protection:
rjmp $
.org 0x01C
Exception_OCD_Breakpoint:
rjmp $
.org 0x020
Exception_Illegal_Opcode:
rjmp $
.org 0x024
Exception_Unimplemented_Instruction:
rjmp $
.org 0x028
Exception_Privilege_Violation:
rjmp $
.org 0x02C
Exception_Floating_Point:
rjmp $
.org 0x030
Exception_Coprocessor_Absent:
rjmp $
.org 0x034
Exception_Data_Address_Read:
rjmp $
.org 0x038
Exception_Data_Address_Write:
rjmp $
.org 0x03C
Exception_DTLB_Protection_Read:
rjmp $
.org 0x040
Exception_DTLB_Protection_Write:
rjmp $
.org 0x044
Exception_DTLB_Modified:
rjmp $
.org 0x050
Exception_ITLB_Miss:
rjmp $
.org 0x060
Exception_DTLB_Miss_Read:
rjmp $
.org 0x070
Exception_DTLB_Miss_Write:
rjmp $
.org 0x100
Exception_Supervisor_Call:
rjmp $
// ============== END OF EXCEPTION TABLE =============
// ============= GENERAL INTERRUPT HANDLER ===========
.balign 4
.irp Level, 0, 1, 2, 3
Exception_INT\Level:
mov r12, \Level
call INTC_GetInterruptHandler
mov pc, r12
.endr
// ========= END OF GENERAL INTERRUPT HANDLER ========
// ====== GENERAL INTERRUPT HANDLER OFFSET TABLE ======
.balign 4
.global Autovector_Table
Autovector_Table:
.irp Level, 0, 1, 2, 3
.word ((AVR32_INTC_INT0 + \Level) << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (Exception_INT\Level - EVBA_Table)
.endr
// === END OF GENERAL INTERRUPT HANDLER OFFSET TABLE ===
#endif

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protocol/lufa/LUFA-git/LUFA/Platform/UC3/InterruptManagement.c Normal file
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/*
LUFA Library
Copyright (C) Dean Camera, 2014.
dean [at] fourwalledcubicle [dot] com
www.lufa-lib.org
*/
/*
Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com)
Permission to use, copy, modify, distribute, and sell this
software and its documentation for any purpose is hereby granted
without fee, provided that the above copyright notice appear in
all copies and that both that the copyright notice and this
permission notice and warranty disclaimer appear in supporting
documentation, and that the name of the author not be used in
advertising or publicity pertaining to distribution of the
software without specific, written prior permission.
The author disclaims all warranties with regard to this
software, including all implied warranties of merchantability
and fitness. In no event shall the author be liable for any
special, indirect or consequential damages or any damages
whatsoever resulting from loss of use, data or profits, whether
in an action of contract, negligence or other tortious action,
arising out of or in connection with the use or performance of
this software.
*/
#include "../../Common/Common.h"
#if (ARCH == ARCH_UC3)
#define __INCLUDE_FROM_INTMANAGEMENT_C
#include "InterruptManagement.h"
/** Interrupt vector table, containing the ISR to call for each interrupt group */
InterruptHandlerPtr_t InterruptHandlers[AVR32_INTC_NUM_INT_GRPS];
/** ISR for unhandled interrupt groups */
ISR(Unhandled_Interrupt)
{
for (;;);
}
InterruptHandlerPtr_t INTC_GetInterruptHandler(const uint_reg_t InterruptLevel)
{
return InterruptHandlers[AVR32_INTC.icr[AVR32_INTC_INT3 - InterruptLevel]];
}
void INTC_Init(void)
{
for (uint8_t InterruptGroup = 0; InterruptGroup < AVR32_INTC_NUM_INT_GRPS; InterruptGroup++)
{
InterruptHandlers[InterruptGroup] = Unhandled_Interrupt;
AVR32_INTC.ipr[InterruptGroup] = Autovector_Table[AVR32_INTC_INT0];
}
__builtin_mtsr(AVR32_EVBA, (uintptr_t)&EVBA_Table);
}
#endif

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/*
LUFA Library
Copyright (C) Dean Camera, 2014.
dean [at] fourwalledcubicle [dot] com
www.lufa-lib.org
*/
/*
Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com)
Permission to use, copy, modify, distribute, and sell this
software and its documentation for any purpose is hereby granted
without fee, provided that the above copyright notice appear in
all copies and that both that the copyright notice and this
permission notice and warranty disclaimer appear in supporting
documentation, and that the name of the author not be used in
advertising or publicity pertaining to distribution of the
software without specific, written prior permission.
The author disclaims all warranties with regard to this
software, including all implied warranties of merchantability
and fitness. In no event shall the author be liable for any
special, indirect or consequential damages or any damages
whatsoever resulting from loss of use, data or profits, whether
in an action of contract, negligence or other tortious action,
arising out of or in connection with the use or performance of
this software.
*/
/** \file
* \brief Interrupt Controller Driver for the AVR32 UC3 microcontrollers.
*
* Interrupt controller driver for the AVR32 UC3 microcontrollers, for the configuration of interrupt
* handlers within the device.
*/
/** \ingroup Group_PlatformDrivers_UC3
* \defgroup Group_PlatformDrivers_UC3Interrupts Interrupt Controller Driver - LUFA/Platform/UC3/InterruptManagement.h
* \brief Interrupt Controller Driver for the AVR32 UC3 microcontrollers.
*
* \section Sec_PlatformDrivers_UC3Interrupts_Dependencies Module Source Dependencies
* The following files must be built with any user project that uses this module:
* - LUFA/Platform/UC3/InterruptManagement.c <i>(Makefile source module name: LUFA_SRC_PLATFORM)</i>
* - LUFA/Platform/UC3/Exception.S <i>(Makefile source module name: LUFA_SRC_PLATFORM)</i>
*
* \section Sec_PlatformDrivers_UC3Interrupts_ModDescription Module Description
* Interrupt controller driver for the AVR32 UC3 microcontrollers, for the configuration of interrupt
* handlers within the device.
*
* Usage Example:
* \code
* #include <LUFA/Platform/UC3/InterruptManagement.h>
*
* ISR(USB_Group_IRQ_Handler)
* {
* // USB group handler code here
* }
*
* void main(void)
* {
* INTC_Init();
* INTC_RegisterGroupHandler(INTC_IRQ_GROUP(AVR32_USBB_IRQ), AVR32_INTC_INT0, USB_Group_IRQ_Handler);
* }
* \endcode
*
* @{
*/
#ifndef _UC3_INTERRUPT_MANAGEMENT_H_
#define _UC3_INTERRUPT_MANAGEMENT_H_
/* Includes: */
#include "../../Common/Common.h"
/* Enable C linkage for C++ Compilers: */
#if defined(__cplusplus)
extern "C" {
#endif
/* Private Interface - For use in library only: */
#if !defined(__DOXYGEN__)
/* Type Defines: */
typedef void (*InterruptHandlerPtr_t)(void);
/* External Variables: */
#if defined(__INCLUDE_FROM_INTMANAGEMENT_C)
extern const void EVBA_Table;
#endif
extern InterruptHandlerPtr_t InterruptHandlers[AVR32_INTC_NUM_INT_GRPS];
extern const uint32_t Autovector_Table[];
#endif
/* Public Interface - May be used in end-application: */
/* Macros: */
/** Converts a given interrupt index into its associated interrupt group.
*
* \param[in] IRQIndex Index of the interrupt request to convert.
*
* \return Interrupt group number associated with the interrupt index.
*/
#define INTC_IRQ_GROUP(IRQIndex) (IRQIndex / 32)
/** Converts a given interrupt index into its associated interrupt line.
*
* \param[in] IRQIndex Index of the interrupt request to convert.
*
* \return Interrupt line number associated with the interrupt index.
*/
#define INTC_IRQ_LINE(IRQIndex) (IRQIndex % 32)
/* Function Prototypes: */
/** Initializes the interrupt controller ready to handle interrupts. This must be called at the
* start of the user program before any interrupts are registered or enabled.
*/
void INTC_Init(void);
/** Retrieves the associated interrupt handler for the interrupt group currently being fired. This
* is called directly from the exception handler routine before dispatching to the ISR.
*
* \param[in] InterruptLevel Priority level of the interrupt.
*
* \return Pointer to the associated interrupt handler function, or NULL if no handler set.
*/
InterruptHandlerPtr_t INTC_GetInterruptHandler(const uint_reg_t InterruptLevel);
/* Inline Functions: */
/** Registers a handler for a given interrupt group. On the AVR32 UC3 devices, interrupts are grouped by
* peripheral. To save on SRAM used, a single ISR handles all interrupt lines within a single group - to
* determine the exact line that has interrupted within the group ISR handler, use \ref INTC_GetGroupInterrupts().
*
* If multiple interrupts with the same group are registered, the last registered handler will become the
* handler called for interrupts raised within that group.
*
* To obtain the group number of a specific interrupt index, use the \ref INTC_IRQ_GROUP() macro.
*
* \param[in] GroupNumber Group number of the interrupt group to register a handler for.
* \param[in] InterruptLevel Priority level for the specified interrupt, a \c AVR32_INTC_INT* mask.
* \param[in] Handler Address of the ISR handler for the interrupt group.
*/
static inline void INTC_RegisterGroupHandler(const uint16_t GroupNumber,
const uint8_t InterruptLevel,
const InterruptHandlerPtr_t Handler) ATTR_ALWAYS_INLINE;
static inline void INTC_RegisterGroupHandler(const uint16_t GroupNumber,
const uint8_t InterruptLevel,
const InterruptHandlerPtr_t Handler)
{
InterruptHandlers[GroupNumber] = Handler;
AVR32_INTC.ipr[GroupNumber] = Autovector_Table[InterruptLevel];
}
/** Retrieves the pending interrupts for a given interrupt group. The result of this function should be masked
* against interrupt request indexes converted to a request line number via the \ref INTC_IRQ_LINE() macro. To
* obtain the group number of a given interrupt request, use the \ref INTC_IRQ_GROUP() macro.
*
* \param[in] GroupNumber Group number of the interrupt group to check.
*
* \return Mask of pending interrupt lines for the given interrupt group.
*/
static inline uint_reg_t INTC_GetGroupInterrupts(const uint16_t GroupNumber) ATTR_ALWAYS_INLINE;
static inline uint_reg_t INTC_GetGroupInterrupts(const uint16_t GroupNumber)
{
return AVR32_INTC.irr[GroupNumber];
}
/* Disable C linkage for C++ Compilers: */
#if defined(__cplusplus)
}
#endif
#endif
/** @} */

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Please note that the UC3 architecture support is EXPERIMENTAL at this time, and may be non-functional/incomplete in some areas. Please refer to the Known Issues section of the LUFA manual.

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/*
LUFA Library
Copyright (C) Dean Camera, 2014.
dean [at] fourwalledcubicle [dot] com
www.lufa-lib.org
*/
/*
Copyright 2014 Dean Camera (dean [at] fourwalledcubicle [dot] com)
Permission to use, copy, modify, distribute, and sell this
software and its documentation for any purpose is hereby granted
without fee, provided that the above copyright notice appear in
all copies and that both that the copyright notice and this
permission notice and warranty disclaimer appear in supporting
documentation, and that the name of the author not be used in
advertising or publicity pertaining to distribution of the
software without specific, written prior permission.
The author disclaims all warranties with regard to this
software, including all implied warranties of merchantability
and fitness. In no event shall the author be liable for any
special, indirect or consequential damages or any damages
whatsoever resulting from loss of use, data or profits, whether
in an action of contract, negligence or other tortious action,
arising out of or in connection with the use or performance of
this software.
*/
/** \file
* \brief Module Clock Driver for the AVR USB XMEGA microcontrollers.
*
* Clock management driver for the AVR USB XMEGA microcontrollers. This driver allows for the configuration
* of the various clocks within the device to clock the various peripherals.
*/
/** \ingroup Group_PlatformDrivers_XMEGA
* \defgroup Group_PlatformDrivers_XMEGAClocks Clock Management Driver - LUFA/Platform/XMEGA/ClockManagement.h
* \brief Module Clock Driver for the AVR USB XMEGA microcontrollers.
*
* \section Sec_PlatformDrivers_XMEGAClocks_Dependencies Module Source Dependencies
* The following files must be built with any user project that uses this module:
* - None
*
* \section Sec_PlatformDrivers_XMEGAClocks_ModDescription Module Description
* Clock management driver for the AVR USB XMEGA microcontrollers. This driver allows for the configuration
* of the various clocks within the device to clock the various peripherals.
*
* Usage Example:
* \code
* #include <LUFA/Platform/XMEGA/ClockManagement.h>
*
* void main(void)
* {
* // Start the PLL to multiply the 2MHz RC oscillator to F_CPU and switch the CPU core to run from it
* XMEGACLK_StartPLL(CLOCK_SRC_INT_RC2MHZ, 2000000, F_CPU);
* XMEGACLK_SetCPUClockSource(CLOCK_SRC_PLL);
*
* // Start the 32MHz internal RC oscillator and start the DFLL to increase it to F_USB using the USB SOF as a reference
* XMEGACLK_StartInternalOscillator(CLOCK_SRC_INT_RC32MHZ);
* XMEGACLK_StartDFLL(CLOCK_SRC_INT_RC32MHZ, DFLL_REF_INT_USBSOF, F_USB);
* }
* \endcode
*
* @{
*/
#ifndef _XMEGA_CLOCK_MANAGEMENT_H_
#define _XMEGA_CLOCK_MANAGEMENT_H_
/* Includes: */
#include "../../Common/Common.h"
/* Enable C linkage for C++ Compilers: */
#if defined(__cplusplus)
extern "C" {
#endif
/* Public Interface - May be used in end-application: */
/* Macros: */
/** Enum for the possible external oscillator frequency ranges. */
enum XMEGA_Extern_OSC_ClockFrequency_t
{
EXOSC_FREQ_2MHZ_MAX = OSC_FRQRANGE_04TO2_gc, /**< External crystal oscillator equal to or slower than 2MHz. */
EXOSC_FREQ_9MHZ_MAX = OSC_FRQRANGE_2TO9_gc, /**< External crystal oscillator equal to or slower than 9MHz. */
EXOSC_FREQ_12MHZ_MAX = OSC_FRQRANGE_9TO12_gc, /**< External crystal oscillator equal to or slower than 12MHz. */
EXOSC_FREQ_16MHZ_MAX = OSC_FRQRANGE_12TO16_gc, /**< External crystal oscillator equal to or slower than 16MHz. */
};
/** Enum for the possible external oscillator startup times. */
enum XMEGA_Extern_OSC_ClockStartup_t
{
EXOSC_START_6CLK = OSC_XOSCSEL_EXTCLK_gc, /**< Wait 6 clock cycles before startup (external clock). */
EXOSC_START_32KCLK = OSC_XOSCSEL_32KHz_gc, /**< Wait 32K clock cycles before startup (32.768KHz crystal). */
EXOSC_START_256CLK = OSC_XOSCSEL_XTAL_256CLK_gc, /**< Wait 256 clock cycles before startup. */
EXOSC_START_1KCLK = OSC_XOSCSEL_XTAL_1KCLK_gc, /**< Wait 1K clock cycles before startup. */
EXOSC_START_16KCLK = OSC_XOSCSEL_XTAL_16KCLK_gc, /**< Wait 16K clock cycles before startup. */
};
/** Enum for the possible module clock sources. */
enum XMEGA_System_ClockSource_t
{
CLOCK_SRC_INT_RC2MHZ = 0, /**< Clock sourced from the Internal 2MHz RC Oscillator clock. */
CLOCK_SRC_INT_RC32MHZ = 1, /**< Clock sourced from the Internal 32MHz RC Oscillator clock. */
CLOCK_SRC_INT_RC32KHZ = 2, /**< Clock sourced from the Internal 32KHz RC Oscillator clock. */
CLOCK_SRC_XOSC = 3, /**< Clock sourced from the External Oscillator clock. */
CLOCK_SRC_PLL = 4, /**< Clock sourced from the Internal PLL clock. */
};
/** Enum for the possible DFLL clock reference sources. */
enum XMEGA_System_DFLLReference_t
{
DFLL_REF_INT_RC32KHZ = 0, /**< Reference clock sourced from the Internal 32KHz RC Oscillator clock. */
DFLL_REF_EXT_RC32KHZ = 1, /**< Reference clock sourced from the External 32KHz RC Oscillator clock connected to TOSC pins. */
DFLL_REF_INT_USBSOF = 2, /**< Reference clock sourced from the USB Start Of Frame packets. */
};
/* Inline Functions: */
/** Write a value to a location protected by the XMEGA CCP protection mechanism. This function uses inline assembly to ensure that
* the protected address is written to within four clock cycles of the CCP key being written.
*
* \param[in] Address Address to write to, a memory address protected by the CCP mechanism
* \param[in] Value Value to write to the protected location
*/
static inline void XMEGACLK_CCP_Write(volatile void* Address, const uint8_t Value) ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;
static inline void XMEGACLK_CCP_Write(volatile void* Address, const uint8_t Value)
{
__asm__ __volatile__ (
"out %0, __zero_reg__" "\n\t" /* Zero RAMPZ using fixed zero value register */
"movw r30, %1" "\n\t" /* Copy address to Z register pair */
"out %2, %3" "\n\t" /* Write key to CCP register */
"st Z, %4" "\n\t" /* Indirectly write value to address */
: /* No output operands */
: /* Input operands: */ "m" (RAMPZ), "e" (Address), "m" (CCP), "r" (CCP_IOREG_gc), "r" (Value)
: /* Clobbered registers: */ "r30", "r31"
);
}
/** Starts the external oscillator of the XMEGA microcontroller, with the given options. This routine blocks until
* the oscillator is ready for use.
*
* \param[in] FreqRange Frequency range of the external oscillator, a value from \ref XMEGA_Extern_OSC_ClockFrequency_t.
* \param[in] Startup Startup time of the external oscillator, a value from \ref XMEGA_Extern_OSC_ClockStartup_t.
*
* \return Boolean \c true if the external oscillator was successfully started, \c false if invalid parameters specified.
*/
static inline bool XMEGACLK_StartExternalOscillator(const uint8_t FreqRange,
const uint8_t Startup) ATTR_ALWAYS_INLINE;
static inline bool XMEGACLK_StartExternalOscillator(const uint8_t FreqRange,
const uint8_t Startup)
{
OSC.XOSCCTRL = (FreqRange | ((Startup == EXOSC_START_32KCLK) ? OSC_X32KLPM_bm : 0) | Startup);
OSC.CTRL |= OSC_XOSCEN_bm;
while (!(OSC.STATUS & OSC_XOSCRDY_bm));
return true;
}
/** Stops the external oscillator of the XMEGA microcontroller. */
static inline void XMEGACLK_StopExternalOscillator(void) ATTR_ALWAYS_INLINE;
static inline void XMEGACLK_StopExternalOscillator(void)
{
OSC.CTRL &= ~OSC_XOSCEN_bm;
}
/** Starts the given internal oscillator of the XMEGA microcontroller, with the given options. This routine blocks until
* the oscillator is ready for use.
*
* \param[in] Source Internal oscillator to start, a value from \ref XMEGA_System_ClockSource_t.
*
* \return Boolean \c true if the internal oscillator was successfully started, \c false if invalid parameters specified.
*/
static inline bool XMEGACLK_StartInternalOscillator(const uint8_t Source) ATTR_ALWAYS_INLINE;
static inline bool XMEGACLK_StartInternalOscillator(const uint8_t Source)
{
switch (Source)
{
case CLOCK_SRC_INT_RC2MHZ:
OSC.CTRL |= OSC_RC2MEN_bm;
while (!(OSC.STATUS & OSC_RC2MRDY_bm));
return true;
case CLOCK_SRC_INT_RC32MHZ:
OSC.CTRL |= OSC_RC32MEN_bm;
while (!(OSC.STATUS & OSC_RC32MRDY_bm));
return true;
case CLOCK_SRC_INT_RC32KHZ:
OSC.CTRL |= OSC_RC32KEN_bm;
while (!(OSC.STATUS & OSC_RC32KRDY_bm));
return true;
default:
return false;
}
}
/** Stops the given internal oscillator of the XMEGA microcontroller.
*
* \param[in] Source Internal oscillator to stop, a value from \ref XMEGA_System_ClockSource_t.
*
* \return Boolean \c true if the internal oscillator was successfully stopped, \c false if invalid parameters specified.
*/
static inline bool XMEGACLK_StopInternalOscillator(const uint8_t Source) ATTR_ALWAYS_INLINE;
static inline bool XMEGACLK_StopInternalOscillator(const uint8_t Source)
{
switch (Source)
{
case CLOCK_SRC_INT_RC2MHZ:
OSC.CTRL &= ~OSC_RC2MEN_bm;
return true;
case CLOCK_SRC_INT_RC32MHZ:
OSC.CTRL &= ~OSC_RC32MEN_bm;
return true;
case CLOCK_SRC_INT_RC32KHZ:
OSC.CTRL &= ~OSC_RC32KEN_bm;
return true;
default:
return false;
}
}
/** Starts the PLL of the XMEGA microcontroller, with the given options. This routine blocks until the PLL is ready for use.
*
* \attention The output frequency must be equal to or greater than the source frequency.
*
* \param[in] Source Clock source for the PLL, a value from \ref XMEGA_System_ClockSource_t.
* \param[in] SourceFreq Frequency of the PLL's clock source, in Hz.
* \param[in] Frequency Target frequency of the PLL's output.
*
* \return Boolean \c true if the PLL was successfully started, \c false if invalid parameters specified.
*/
static inline bool XMEGACLK_StartPLL(const uint8_t Source,
const uint32_t SourceFreq,
const uint32_t Frequency) ATTR_ALWAYS_INLINE;
static inline bool XMEGACLK_StartPLL(const uint8_t Source,
const uint32_t SourceFreq,
const uint32_t Frequency)
{
uint8_t MulFactor = (Frequency / SourceFreq);
if (SourceFreq > Frequency)
return false;
if (MulFactor > 31)
return false;
switch (Source)
{
case CLOCK_SRC_INT_RC2MHZ:
OSC.PLLCTRL = (OSC_PLLSRC_RC2M_gc | MulFactor);
break;
case CLOCK_SRC_INT_RC32MHZ:
OSC.PLLCTRL = (OSC_PLLSRC_RC32M_gc | MulFactor);
break;
case CLOCK_SRC_XOSC:
OSC.PLLCTRL = (OSC_PLLSRC_XOSC_gc | MulFactor);
break;
default:
return false;
}
OSC.CTRL |= OSC_PLLEN_bm;
while (!(OSC.STATUS & OSC_PLLRDY_bm));
return true;
}
/** Stops the PLL of the XMEGA microcontroller. */
static inline void XMEGACLK_StopPLL(void) ATTR_ALWAYS_INLINE;
static inline void XMEGACLK_StopPLL(void)
{
OSC.CTRL &= ~OSC_PLLEN_bm;
}
/** Starts the DFLL of the XMEGA microcontroller, with the given options.
*
* \param[in] Source RC Clock source for the DFLL, a value from \ref XMEGA_System_ClockSource_t.
* \param[in] Reference Reference clock source for the DFLL, an value from \ref XMEGA_System_DFLLReference_t.
* \param[in] Frequency Target frequency of the DFLL's output.
*
* \return Boolean \c true if the DFLL was successfully started, \c false if invalid parameters specified.
*/
static inline bool XMEGACLK_StartDFLL(const uint8_t Source,
const uint8_t Reference,
const uint32_t Frequency) ATTR_ALWAYS_INLINE;
static inline bool XMEGACLK_StartDFLL(const uint8_t Source,
const uint8_t Reference,
const uint32_t Frequency)
{
uint16_t DFLLCompare = (Frequency / 1024);
switch (Source)
{
case CLOCK_SRC_INT_RC2MHZ:
OSC.DFLLCTRL |= (Reference << OSC_RC2MCREF_bp);
DFLLRC2M.COMP1 = (DFLLCompare & 0xFF);
DFLLRC2M.COMP2 = (DFLLCompare >> 8);
DFLLRC2M.CTRL = DFLL_ENABLE_bm;
break;
case CLOCK_SRC_INT_RC32MHZ:
OSC.DFLLCTRL |= (Reference << OSC_RC32MCREF_gp);
DFLLRC32M.COMP1 = (DFLLCompare & 0xFF);
DFLLRC32M.COMP2 = (DFLLCompare >> 8);
if (Reference == DFLL_REF_INT_USBSOF)
{
NVM.CMD = NVM_CMD_READ_CALIB_ROW_gc;
DFLLRC32M.CALA = pgm_read_byte(offsetof(NVM_PROD_SIGNATURES_t, USBRCOSCA));
DFLLRC32M.CALB = pgm_read_byte(offsetof(NVM_PROD_SIGNATURES_t, USBRCOSC));
NVM.CMD = 0;
}
DFLLRC32M.CTRL = DFLL_ENABLE_bm;
break;
default:
return false;
}
return true;
}
/** Stops the given DFLL of the XMEGA microcontroller.
*
* \param[in] Source RC Clock source for the DFLL to be stopped, a value from \ref XMEGA_System_ClockSource_t.
*
* \return Boolean \c true if the DFLL was successfully stopped, \c false if invalid parameters specified.
*/
static inline bool XMEGACLK_StopDFLL(const uint8_t Source) ATTR_ALWAYS_INLINE;
static inline bool XMEGACLK_StopDFLL(const uint8_t Source)
{
switch (Source)
{
case CLOCK_SRC_INT_RC2MHZ:
DFLLRC2M.CTRL = 0;
break;
case CLOCK_SRC_INT_RC32MHZ:
DFLLRC32M.CTRL = 0;
break;
default:
return false;
}
return true;
}
/** Sets the clock source for the main microcontroller core. The given clock source should be configured
* and ready for use before this function is called.
*
* \param[in] Source Clock source for the CPU core, a value from \ref XMEGA_System_ClockSource_t.
*
* \return Boolean \c true if the CPU core clock was successfully altered, \c false if invalid parameters specified.
*/
static inline bool XMEGACLK_SetCPUClockSource(const uint8_t Source) ATTR_ALWAYS_INLINE;
static inline bool XMEGACLK_SetCPUClockSource(const uint8_t Source)
{
uint8_t ClockSourceMask = 0;
switch (Source)
{
case CLOCK_SRC_INT_RC2MHZ:
ClockSourceMask = CLK_SCLKSEL_RC2M_gc;
break;
case CLOCK_SRC_INT_RC32MHZ:
ClockSourceMask = CLK_SCLKSEL_RC32M_gc;
break;
case CLOCK_SRC_INT_RC32KHZ:
ClockSourceMask = CLK_SCLKSEL_RC32K_gc;
break;
case CLOCK_SRC_XOSC:
ClockSourceMask = CLK_SCLKSEL_XOSC_gc;
break;
case CLOCK_SRC_PLL:
ClockSourceMask = CLK_SCLKSEL_PLL_gc;
break;
default:
return false;
}
uint_reg_t CurrentGlobalInt = GetGlobalInterruptMask();
GlobalInterruptDisable();
XMEGACLK_CCP_Write(&CLK.CTRL, ClockSourceMask);
SetGlobalInterruptMask(CurrentGlobalInt);
Delay_MS(1);
return (CLK.CTRL == ClockSourceMask);
}
/* Disable C linkage for C++ Compilers: */
#if defined(__cplusplus)
}
#endif
#endif
/** @} */

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Please note that the XMEGA architecture support is EXPERIMENTAL at this time, and may be non-functional/incomplete in some areas. Please refer to the Known Issues section of the LUFA manual.