[Core] Add support for RISC-V builds and GD32VF103 MCU (#12508)
* Add support for RISC-V builds and GD32VF103 MCU * Add toolchain selection in chibios.mk based on the mcu selected in mcu_selection.mk * Reorder and added comments to chibios.mk to have a streamlined makefile * Add GD32VF103 mcu to possible targets for QMK. * Add STM32 compatibility for GD32VF103 MCU, this is hacky but more efficent then rewriting every driver. * Add GigaDevice DFU bootloader as flash target, please note that dfu-util of at least version 0.10 is needed. * Add analog driver compatibility * Add apa102 bitbang driver compatibility * Add ws2812 bitbang driver compatibility * Add eeprom in flash emulation compatibility * Allow faster re-builds with ccache * Add SiPeed Longan Nano to platform files * Add SiPeed Longan Nano Onekeys * Make quine compatible with other bootloaders * Support builds with picolibc * Add risc-v toolchain to arch and debian/ubuntu scripts
This commit is contained in:
parent
7e3ff206b8
commit
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31 changed files with 900 additions and 122 deletions
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# List of all the board related files.
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BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/SIPEED_LONGAN_NANO/board.c
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# Required include directories
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BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/SIPEED_LONGAN_NANO
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# Shared variables
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ALLCSRC += $(BOARDSRC)
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ALLINC += $(BOARDINC)
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23
platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/chconf.h
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platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/chconf.h
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/* Copyright 2021 QMK
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* To compile the ChibiOS syscall stubs with picolibc
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* the _reent struct has to be defined. */
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#if !defined(_FROM_ASM_) && defined(USE_PICOLIBC)
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struct _reent;
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#endif
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#include_next <chconf.h>
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302
platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/mcuconf.h
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302
platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/mcuconf.h
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2021 Stefan Kerkmann
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#pragma once
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#define GD32VF103_MCUCONF
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#define GD32VF103CB
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/*
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* GD32VF103 drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 0...15 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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/*
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* HAL driver system settings.
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*/
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#if defined(OVERCLOCK_120MHZ)
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/* (8MHz / 2) * 30 = 120MHz Sysclock */
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#define GD32_ALLOW_120MHZ_SYSCLK
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#define GD32_PLLMF_VALUE 30
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#define GD32_USBFSPSC GD32_USBFSPSC_DIV2P5
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#else
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/* (8MHz / 2) * 24 = 96MHz Sysclock */
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#define GD32_PLLMF_VALUE 24
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#define GD32_USBFSPSC GD32_USBFSPSC_DIV2
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#endif
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#define GD32_NO_INIT FALSE
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#define GD32_IRC8M_ENABLED TRUE
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#define GD32_IRC40K_ENABLED FALSE
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#define GD32_HXTAL_ENABLED TRUE
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#define GD32_LXTAL_ENABLED FALSE
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#define GD32_SCS GD32_SCS_PLL
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#define GD32_PLLSEL GD32_PLLSEL_PREDV0
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#define GD32_PREDV0SEL GD32_PREDV0SEL_HXTAL
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#define GD32_PREDV0_VALUE 2
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#define GD32_PREDV1_VALUE 2
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#define GD32_PLL1MF_VALUE 14
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#define GD32_PLL2MF_VALUE 13
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#define GD32_AHBPSC GD32_AHBPSC_DIV1
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#define GD32_APB1PSC GD32_APB1PSC_DIV2
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#define GD32_APB2PSC GD32_APB2PSC_DIV1
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#define GD32_ADCPSC GD32_ADCPSC_DIV16
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#define GD32_USB_CLOCK_REQUIRED TRUE
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#define GD32_I2S_CLOCK_REQUIRED FALSE
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#define GD32_CKOUT0SEL GD32_CKOUT0SEL_NOCLOCK
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#define GD32_RTCSRC GD32_RTCSRC_NOCLOCK
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#define GD32_PVD_ENABLE FALSE
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#define GD32_LVDT GD32_LVDT_LEV0
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/*
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* ECLIC system settings.
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*/
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#define ECLIC_TRIGGER_DEFAULT ECLIC_POSTIVE_EDGE_TRIGGER
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#define ECLIC_DMA_TRIGGER ECLIC_TRIGGER_DEFAULT
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/*
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* IRQ system settings.
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*/
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#define GD32_IRQ_EXTI0_PRIORITY 6
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#define GD32_IRQ_EXTI1_PRIORITY 6
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#define GD32_IRQ_EXTI2_PRIORITY 6
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#define GD32_IRQ_EXTI3_PRIORITY 6
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#define GD32_IRQ_EXTI4_PRIORITY 6
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#define GD32_IRQ_EXTI5_9_PRIORITY 6
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#define GD32_IRQ_EXTI10_15_PRIORITY 6
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#define GD32_IRQ_EXTI0_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_EXTI1_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_EXTI2_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_EXTI3_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_EXTI4_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_EXTI5_9_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_EXTI10_15_TRIGGER ECLIC_TRIGGER_DEFAULT
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/*
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* ADC driver system settings.
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*/
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#define GD32_ADC_USE_ADC0 FALSE
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#define GD32_ADC_ADC0_DMA_PRIORITY 2
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#define GD32_ADC_ADC0_IRQ_PRIORITY 6
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/*
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* CAN driver system settings.
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*/
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#define GD32_CAN_USE_CAN0 FALSE
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#define GD32_CAN_CAN0_IRQ_PRIORITY 11
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#define GD32_CAN_USE_CAN1 FALSE
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#define GD32_CAN_CAN1_IRQ_PRIORITY 11
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#define GD32_CAN_CAN0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_CAN_CAN1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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/*
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* CRC driver system settings.
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*/
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#define GD32_CRC_USE_CRC0 FALSE
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#define GD32_CRC_CRC0_DMA_IRQ_PRIORITY 14
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#define GD32_CRC_CRC0_DMA_PRIORITY 2
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#define GD32_CRC_CRC0_DMA_STREAM GD32_DMA_STREAM_ID(0, 0)
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#define CRC_USE_DMA FALSE
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#define CRCSW_USE_CRC1 FALSE
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#define CRCSW_CRC32_TABLE FALSE
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#define CRCSW_CRC16_TABLE FALSE
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#define CRCSW_PROGRAMMABLE FALSE
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/*
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* DAC driver system settings.
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*/
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#define GD32_DAC_USE_DAC_CH1 FALSE
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#define GD32_DAC_USE_DAC_CH2 FALSE
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/*
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* GPT driver system settings.
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*/
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#define GD32_GPT_USE_TIM0 FALSE
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#define GD32_GPT_USE_TIM1 FALSE
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#define GD32_GPT_USE_TIM2 FALSE
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#define GD32_GPT_USE_TIM3 FALSE
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#define GD32_GPT_USE_TIM4 FALSE
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#define GD32_GPT_TIM0_IRQ_PRIORITY 7
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#define GD32_GPT_TIM1_IRQ_PRIORITY 7
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#define GD32_GPT_TIM2_IRQ_PRIORITY 7
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#define GD32_GPT_TIM3_IRQ_PRIORITY 7
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#define GD32_GPT_TIM4_IRQ_PRIORITY 7
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#define GD32_GPT_TIM0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM5_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM6_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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/*
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* I2S driver system settings.
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*/
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#define GD32_I2S_USE_SPI1 FALSE
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#define GD32_I2S_USE_SPI2 FALSE
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#define GD32_I2S_SPI1_IRQ_PRIORITY 10
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#define GD32_I2S_SPI2_IRQ_PRIORITY 10
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#define GD32_I2S_SPI1_DMA_PRIORITY 1
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#define GD32_I2S_SPI2_DMA_PRIORITY 1
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#define GD32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
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/*
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* I2C driver system settings.
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*/
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#define GD32_I2C_USE_I2C0 FALSE
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#define GD32_I2C_USE_I2C1 FALSE
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#define GD32_I2C_BUSY_TIMEOUT 50
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#define GD32_I2C_I2C0_IRQ_PRIORITY 10
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#define GD32_I2C_I2C1_IRQ_PRIORITY 5
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#define GD32_I2C_I2C0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_I2C_I2C1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_I2C_I2C0_DMA_PRIORITY 2
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#define GD32_I2C_I2C1_DMA_PRIORITY 2
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#define GD32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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* ICU driver system settings.
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*/
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#define GD32_ICU_USE_TIM0 FALSE
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#define GD32_ICU_USE_TIM1 FALSE
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#define GD32_ICU_USE_TIM2 FALSE
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#define GD32_ICU_USE_TIM3 FALSE
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#define GD32_ICU_USE_TIM4 FALSE
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#define GD32_ICU_TIM0_IRQ_PRIORITY 7
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#define GD32_ICU_TIM1_IRQ_PRIORITY 7
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#define GD32_ICU_TIM2_IRQ_PRIORITY 7
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#define GD32_ICU_TIM3_IRQ_PRIORITY 7
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#define GD32_ICU_TIM4_IRQ_PRIORITY 7
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#define GD32_ICU_TIM0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_ICU_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_ICU_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_ICU_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_ICU_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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/*
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* PWM driver system settings.
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*/
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#define GD32_PWM_USE_ADVANCED FALSE
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#define GD32_PWM_USE_TIM0 FALSE
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#define GD32_PWM_USE_TIM1 FALSE
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#define GD32_PWM_USE_TIM2 FALSE
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#define GD32_PWM_USE_TIM3 FALSE
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#define GD32_PWM_USE_TIM4 FALSE
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#define GD32_PWM_TIM0_IRQ_PRIORITY 10
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#define GD32_PWM_TIM1_IRQ_PRIORITY 10
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#define GD32_PWM_TIM2_IRQ_PRIORITY 10
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#define GD32_PWM_TIM3_IRQ_PRIORITY 10
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#define GD32_PWM_TIM4_IRQ_PRIORITY 10
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#define GD32_PWM_TIM0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_PWM_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_PWM_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_PWM_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_PWM_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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/*
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* RTC driver system settings.
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*/
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#define GD32_RTC_IRQ_PRIORITY 15
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#define GD32_RTC_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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/*
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* SERIAL driver system settings.
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*/
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#define GD32_SERIAL_USE_USART0 FALSE
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#define GD32_SERIAL_USE_USART1 FALSE
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#define GD32_SERIAL_USE_USART2 FALSE
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#define GD32_SERIAL_USE_UART3 FALSE
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#define GD32_SERIAL_USE_UART4 FALSE
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#define GD32_SERIAL_USART0_PRIORITY 10
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#define GD32_SERIAL_USART1_PRIORITY 10
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#define GD32_SERIAL_USART2_PRIORITY 10
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#define GD32_SERIAL_UART3_PRIORITY 10
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#define GD32_SERIAL_UART4_PRIORITY 10
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#define GD32_SERIAL_USART0_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_SERIAL_USART1_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_SERIAL_USART2_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_SERIAL_UART3_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_SERIAL_UART4_TRIGGER ECLIC_TRIGGER_DEFAULT
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/*
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* SPI driver system settings.
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*/
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#define GD32_SPI_USE_SPI0 FALSE
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#define GD32_SPI_USE_SPI1 FALSE
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#define GD32_SPI_USE_SPI2 FALSE
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#define GD32_SPI_SPI0_DMA_PRIORITY 1
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#define GD32_SPI_SPI1_DMA_PRIORITY 1
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#define GD32_SPI_SPI2_DMA_PRIORITY 1
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#define GD32_SPI_SPI0_IRQ_PRIORITY 10
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#define GD32_SPI_SPI1_IRQ_PRIORITY 10
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#define GD32_SPI_SPI2_IRQ_PRIORITY 10
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#define GD32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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/*
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* ST driver system settings.
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*/
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#define GD32_ST_IRQ_PRIORITY 10
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#define GD32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_ST_USE_TIMER 1
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/*
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* UART driver system settings.
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*/
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#define GD32_UART_USE_USART0 FALSE
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#define GD32_UART_USE_USART1 FALSE
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#define GD32_UART_USE_USART2 FALSE
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#define GD32_UART_USE_UART3 FALSE
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#define GD32_UART_USE_UART4 FALSE
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#define GD32_UART_USART0_IRQ_PRIORITY 10
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#define GD32_UART_USART1_IRQ_PRIORITY 10
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#define GD32_UART_USART2_IRQ_PRIORITY 10
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#define GD32_UART_UART3_IRQ_PRIORITY 10
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#define GD32_UART_UART4_IRQ_PRIORITY 10
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#define GD32_UART_USART0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_UART_USART1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_UART_USART2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_UART_UART3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_UART_UART4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_UART_USART0_DMA_PRIORITY 3
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#define GD32_UART_USART1_DMA_PRIORITY 3
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#define GD32_UART_USART2_DMA_PRIORITY 3
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#define GD32_UART_UART3_DMA_PRIORITY 3
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#define GD32_UART_UART4_DMA_PRIORITY 3
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#define GD32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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/*
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* USB driver system settings.
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*/
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#define GD32_USB_USE_USBFS TRUE
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#define GD32_USB_USBFS_IRQ_PRIORITY 10
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#define GD32_USB_USBFS_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_USB_USBFS_RX_FIFO_SIZE 256
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/*
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* WDG driver system settings.
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*/
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#define GD32_WDG_USE_FWDGT FALSE
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// Otherwise assume V3
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#if defined(STM32F0XX) || defined(STM32L0XX)
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# define USE_ADCV1
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#elif defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX)
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#elif defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX) || defined(GD32VF103)
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# define USE_ADCV2
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#endif
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/* User configurable ADC options */
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#ifndef ADC_COUNT
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# if defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX)
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# if defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX) || defined(GD32VF103)
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# define ADC_COUNT 1
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# elif defined(STM32F3XX)
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# define ADC_COUNT 4
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@ -122,8 +122,8 @@ static ADCConversionGroup adcConversionGroup = {
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.cfgr1 = ADC_CFGR1_CONT | ADC_RESOLUTION,
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.smpr = ADC_SAMPLING_RATE,
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#elif defined(USE_ADCV2)
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# if !defined(STM32F1XX)
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.cr2 = ADC_CR2_SWSTART, // F103 seem very unhappy with, F401 seems very unhappy without...
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# if !defined(STM32F1XX) && !defined(GD32VF103)
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.cr2 = ADC_CR2_SWSTART, // F103 seem very unhappy with, F401 seems very unhappy without...
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# endif
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.smpr2 = ADC_SMPR2_SMP_AN0(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN1(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN2(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN3(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN4(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN5(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN6(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN7(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN8(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN9(ADC_SAMPLING_RATE),
|
||||
.smpr1 = ADC_SMPR1_SMP_AN10(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN11(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN12(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN13(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN14(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN15(ADC_SAMPLING_RATE),
|
||||
|
@ -220,7 +220,7 @@ __attribute__((weak)) adc_mux pinToMux(pin_t pin) {
|
|||
case F9: return TO_MUX( ADC_CHANNEL_IN7, 2 );
|
||||
case F10: return TO_MUX( ADC_CHANNEL_IN8, 2 );
|
||||
# endif
|
||||
#elif defined(STM32F1XX)
|
||||
#elif defined(STM32F1XX) || defined(GD32VF103)
|
||||
case A0: return TO_MUX( ADC_CHANNEL_IN0, 0 );
|
||||
case A1: return TO_MUX( ADC_CHANNEL_IN1, 0 );
|
||||
case A2: return TO_MUX( ADC_CHANNEL_IN2, 0 );
|
||||
|
|
|
@ -6,7 +6,7 @@
|
|||
/* Adapted from https://github.com/bigjosh/SimpleNeoPixelDemo/ */
|
||||
|
||||
#ifndef NOP_FUDGE
|
||||
# if defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F3XX) || defined(STM32F4XX) || defined(STM32L0XX)
|
||||
# if defined(STM32F0XX) || defined(STM32F1XX) || defined(GD32VF103) || defined(STM32F3XX) || defined(STM32F4XX) || defined(STM32L0XX)
|
||||
# define NOP_FUDGE 0.4
|
||||
# else
|
||||
# error("NOP_FUDGE configuration required")
|
||||
|
|
|
@ -82,6 +82,8 @@ else ifeq ($(strip $(MCU_FAMILY)),MIMXRT1062)
|
|||
$(UNSYNC_OUTPUT_CMD) && $(call EXEC_TEENSY)
|
||||
else ifeq ($(strip $(MCU_FAMILY)),STM32)
|
||||
$(UNSYNC_OUTPUT_CMD) && $(call EXEC_DFU_UTIL)
|
||||
else ifeq ($(strip $(MCU_FAMILY)),GD32V)
|
||||
$(UNSYNC_OUTPUT_CMD) && $(call EXEC_DFU_UTIL)
|
||||
else
|
||||
$(PRINT_OK); $(SILENT) || printf "$(MSG_FLASH_BOOTLOADER)"
|
||||
endif
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue