[Core] Add Raspberry Pi RP2040 support (#14877)
* Disable RESET keycode because of naming conflicts * Add Pico SDK as submodule * Add RP2040 build support to QMK * Adjust USB endpoint structs for RP2040 * Add RP2040 bootloader and double-tap reset routine * Add generic and pro micro RP2040 boards * Add RP2040 onekey keyboard * Add WS2812 PIO DMA enabled driver and documentation Supports regular and open-drain output configuration. RP2040 GPIOs are sadly not 5V tolerant, so this is a bit use-less or needs extra hardware or you take the risk to fry your hardware. * Adjust SIO Driver for RP2040 * Adjust I2C Driver for RP2040 * Adjust SPI Driver for RP2040 * Add PIO serial driver and documentation * Add general RP2040 documentation * Apply suggestions from code review Co-authored-by: Nick Brassel <nick@tzarc.org> Co-authored-by: Nick Brassel <nick@tzarc.org>
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43 changed files with 2026 additions and 96 deletions
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@ -20,7 +20,7 @@
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static pin_t currentSlavePin = NO_PIN;
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#if defined(K20x) || defined(KL2x)
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#if defined(K20x) || defined(KL2x) || defined(RP2040)
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static SPIConfig spiConfig = {NULL, 0, 0, 0};
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#else
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static SPIConfig spiConfig = {false, NULL, 0, 0, 0, 0};
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@ -167,7 +167,36 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
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spiConfig.SPI_CPOL = SPI_CPOL_High;
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break;
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}
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#elif defined(MCU_RP)
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if (lsbFirst) {
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osalDbgAssert(lsbFirst == false, "RP2040s PrimeCell SPI implementation does not support sending LSB first.");
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}
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// Motorola frame format and 8bit transfer data size.
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spiConfig.SSPCR0 = SPI_SSPCR0_FRF_MOTOROLA | SPI_SSPCR0_DSS_8BIT;
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// Serial output clock = (ck_sys or ck_peri) / (SSPCPSR->CPSDVSR * (1 +
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// SSPCR0->SCR)). SCR is always set to zero, as QMK SPI API expects the
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// passed divisor to be the only value to divide the input clock by.
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spiConfig.SSPCPSR = roundedDivisor; // Even number from 2 to 254
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switch (mode) {
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case 0:
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spiConfig.SSPCR0 &= ~SPI_SSPCR0_SPO; // Clock polarity: low
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spiConfig.SSPCR0 &= ~SPI_SSPCR0_SPH; // Clock phase: sample on first edge
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break;
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case 1:
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spiConfig.SSPCR0 &= ~SPI_SSPCR0_SPO; // Clock polarity: low
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spiConfig.SSPCR0 |= SPI_SSPCR0_SPH; // Clock phase: sample on second edge transition
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break;
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case 2:
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spiConfig.SSPCR0 |= SPI_SSPCR0_SPO; // Clock polarity: high
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spiConfig.SSPCR0 &= ~SPI_SSPCR0_SPH; // Clock phase: sample on first edge
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break;
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case 3:
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spiConfig.SSPCR0 |= SPI_SSPCR0_SPO; // Clock polarity: high
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spiConfig.SSPCR0 |= SPI_SSPCR0_SPH; // Clock phase: sample on second edge transition
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break;
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}
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#else
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spiConfig.cr1 = 0;
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