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Add customisable EEPROM driver selection (#7274)

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- uprintf -> dprintf
- Fix atsam "vendor" eeprom.
- Bump Kinetis K20x to 64 bytes, too.
- Rollback Kinetis to 32 bytes as partitioning can only be done once. Add warning about changing the value.
- Change RAM-backed "fake" EEPROM implementations to match eeconfig's current usage.
- Add 24LC128 by request.
This commit is contained in:
Nick Brassel 2019-11-06 08:04:50 +11:00
parent 6ff093efbe
commit d13ada1162
20 changed files with 616 additions and 52 deletions
Download patch file Download diff file Expand all files Collapse all files

6
tmk_core/common/chibios/eeprom_stm32.c
View file

@ -173,7 +173,7 @@ void eeprom_update_dword(uint32_t *Address, uint32_t Value) {
}
}
void eeprom_read_block(void *buf, const void *addr, uint32_t len) {
void eeprom_read_block(void *buf, const void *addr, size_t len) {
const uint8_t *p = (const uint8_t *)addr;
uint8_t * dest = (uint8_t *)buf;
while (len--) {
@ -181,7 +181,7 @@ void eeprom_read_block(void *buf, const void *addr, uint32_t len) {
}
}
void eeprom_write_block(const void *buf, void *addr, uint32_t len) {
void eeprom_write_block(const void *buf, void *addr, size_t len) {
uint8_t * p = (uint8_t *)addr;
const uint8_t *src = (const uint8_t *)buf;
while (len--) {
@ -189,7 +189,7 @@ void eeprom_write_block(const void *buf, void *addr, uint32_t len) {
}
}
void eeprom_update_block(const void *buf, void *addr, uint32_t len) {
void eeprom_update_block(const void *buf, void *addr, size_t len) {
uint8_t * p = (uint8_t *)addr;
const uint8_t *src = (const uint8_t *)buf;
while (len--) {

25
tmk_core/common/chibios/eeprom_teensy.c
View file

@ -50,7 +50,17 @@
// (aligned to 2 or 4 byte boundaries) has twice the endurance
// compared to writing 8 bit bytes.
//
# define EEPROM_SIZE 32
# ifndef EEPROM_SIZE
# define EEPROM_SIZE 32
# endif
/*
^^^ Here be dragons:
NXP AppNote AN4282 section 3.1 states that partitioning must only be done once.
Once EEPROM partitioning is done, the size is locked to this initial configuration.
Attempts to modify the EEPROM_SIZE setting may brick your board.
*/
// Writing unaligned 16 or 32 bit data is handled automatically when
// this is defined, but at a cost of extra code size. Without this,
@ -517,8 +527,11 @@ void eeprom_write_block(const void *buf, void *addr, uint32_t len) {
#else
// No EEPROM supported, so emulate it
# define EEPROM_SIZE 32
static uint8_t buffer[EEPROM_SIZE];
# ifndef EEPROM_SIZE
# include "eeconfig.h"
# define EEPROM_SIZE (((EECONFIG_SIZE+3)/4)*4) // based off eeconfig's current usage, aligned to 4-byte sizes, to deal with LTO
# endif
__attribute__((aligned(4))) static uint8_t buffer[EEPROM_SIZE];
uint8_t eeprom_read_byte(const uint8_t *addr) {
uint32_t offset = (uint32_t)addr;
@ -540,7 +553,7 @@ uint32_t eeprom_read_dword(const uint32_t *addr) {
return eeprom_read_byte(p) | (eeprom_read_byte(p + 1) << 8) | (eeprom_read_byte(p + 2) << 16) | (eeprom_read_byte(p + 3) << 24);
}
void eeprom_read_block(void *buf, const void *addr, uint32_t len) {
void eeprom_read_block(void *buf, const void *addr, size_t len) {
const uint8_t *p = (const uint8_t *)addr;
uint8_t * dest = (uint8_t *)buf;
while (len--) {
@ -562,7 +575,7 @@ void eeprom_write_dword(uint32_t *addr, uint32_t value) {
eeprom_write_byte(p, value >> 24);
}
void eeprom_write_block(const void *buf, void *addr, uint32_t len) {
void eeprom_write_block(const void *buf, void *addr, size_t len) {
uint8_t * p = (uint8_t *)addr;
const uint8_t *src = (const uint8_t *)buf;
while (len--) {
@ -589,7 +602,7 @@ void eeprom_update_dword(uint32_t *addr, uint32_t value) {
eeprom_write_byte(p, value >> 24);
}
void eeprom_update_block(const void *buf, void *addr, uint32_t len) {
void eeprom_update_block(const void *buf, void *addr, size_t len) {
uint8_t * p = (uint8_t *)addr;
const uint8_t *src = (const uint8_t *)buf;
while (len--) {