clang-format changes
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skullY
skullydazed
parent
61af76a10d
commit
b624f32f94
502 changed files with 32259 additions and 39062 deletions
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@ -34,98 +34,83 @@ static uint8_t i2c_address;
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static const I2CConfig i2cconfig = {
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#ifdef USE_I2CV1
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I2C1_OPMODE,
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I2C1_CLOCK_SPEED,
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I2C1_DUTY_CYCLE,
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I2C1_OPMODE,
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I2C1_CLOCK_SPEED,
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I2C1_DUTY_CYCLE,
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#else
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STM32_TIMINGR_PRESC(I2C1_TIMINGR_PRESC) |
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STM32_TIMINGR_SCLDEL(I2C1_TIMINGR_SCLDEL) | STM32_TIMINGR_SDADEL(I2C1_TIMINGR_SDADEL) |
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STM32_TIMINGR_SCLH(I2C1_TIMINGR_SCLH) | STM32_TIMINGR_SCLL(I2C1_TIMINGR_SCLL),
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0,
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0
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STM32_TIMINGR_PRESC(I2C1_TIMINGR_PRESC) | STM32_TIMINGR_SCLDEL(I2C1_TIMINGR_SCLDEL) | STM32_TIMINGR_SDADEL(I2C1_TIMINGR_SDADEL) | STM32_TIMINGR_SCLH(I2C1_TIMINGR_SCLH) | STM32_TIMINGR_SCLL(I2C1_TIMINGR_SCLL), 0, 0
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#endif
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};
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static i2c_status_t chibios_to_qmk(const msg_t* status) {
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switch (*status) {
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case I2C_NO_ERROR:
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return I2C_STATUS_SUCCESS;
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case I2C_TIMEOUT:
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return I2C_STATUS_TIMEOUT;
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// I2C_BUS_ERROR, I2C_ARBITRATION_LOST, I2C_ACK_FAILURE, I2C_OVERRUN, I2C_PEC_ERROR, I2C_SMB_ALERT
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default:
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return I2C_STATUS_ERROR;
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}
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switch (*status) {
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case I2C_NO_ERROR:
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return I2C_STATUS_SUCCESS;
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case I2C_TIMEOUT:
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return I2C_STATUS_TIMEOUT;
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// I2C_BUS_ERROR, I2C_ARBITRATION_LOST, I2C_ACK_FAILURE, I2C_OVERRUN, I2C_PEC_ERROR, I2C_SMB_ALERT
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default:
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return I2C_STATUS_ERROR;
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}
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}
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__attribute__ ((weak))
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void i2c_init(void)
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{
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// Try releasing special pins for a short time
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palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_INPUT);
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palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_INPUT);
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__attribute__((weak)) void i2c_init(void) {
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// Try releasing special pins for a short time
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palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_INPUT);
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palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_INPUT);
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chThdSleepMilliseconds(10);
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chThdSleepMilliseconds(10);
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#ifdef USE_I2CV1
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palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
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palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
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palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
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palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
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#else
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palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_ALTERNATE(I2C1_SCL_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
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palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_ALTERNATE(I2C1_SDA_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
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palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_ALTERNATE(I2C1_SCL_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
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palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_ALTERNATE(I2C1_SDA_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
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#endif
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//i2cInit(); //This is invoked by halInit() so no need to redo it.
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// i2cInit(); //This is invoked by halInit() so no need to redo it.
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}
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i2c_status_t i2c_start(uint8_t address)
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{
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i2c_address = address;
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i2cStart(&I2C_DRIVER, &i2cconfig);
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return I2C_STATUS_SUCCESS;
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i2c_status_t i2c_start(uint8_t address) {
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i2c_address = address;
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i2cStart(&I2C_DRIVER, &i2cconfig);
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return I2C_STATUS_SUCCESS;
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}
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i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout)
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{
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i2c_address = address;
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i2cStart(&I2C_DRIVER, &i2cconfig);
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msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), data, length, 0, 0, MS2ST(timeout));
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return chibios_to_qmk(&status);
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i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout) {
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i2c_address = address;
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i2cStart(&I2C_DRIVER, &i2cconfig);
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msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), data, length, 0, 0, MS2ST(timeout));
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return chibios_to_qmk(&status);
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}
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i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout)
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{
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i2c_address = address;
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i2cStart(&I2C_DRIVER, &i2cconfig);
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msg_t status = i2cMasterReceiveTimeout(&I2C_DRIVER, (i2c_address >> 1), data, length, MS2ST(timeout));
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return chibios_to_qmk(&status);
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i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout) {
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i2c_address = address;
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i2cStart(&I2C_DRIVER, &i2cconfig);
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msg_t status = i2cMasterReceiveTimeout(&I2C_DRIVER, (i2c_address >> 1), data, length, MS2ST(timeout));
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return chibios_to_qmk(&status);
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}
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i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout)
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{
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i2c_address = devaddr;
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i2cStart(&I2C_DRIVER, &i2cconfig);
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i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout) {
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i2c_address = devaddr;
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i2cStart(&I2C_DRIVER, &i2cconfig);
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uint8_t complete_packet[length + 1];
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for(uint8_t i = 0; i < length; i++)
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{
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complete_packet[i+1] = data[i];
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}
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complete_packet[0] = regaddr;
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uint8_t complete_packet[length + 1];
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for (uint8_t i = 0; i < length; i++) {
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complete_packet[i + 1] = data[i];
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}
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complete_packet[0] = regaddr;
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msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), complete_packet, length + 1, 0, 0, MS2ST(timeout));
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return chibios_to_qmk(&status);
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msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), complete_packet, length + 1, 0, 0, MS2ST(timeout));
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return chibios_to_qmk(&status);
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}
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i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout)
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{
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i2c_address = devaddr;
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i2cStart(&I2C_DRIVER, &i2cconfig);
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msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), ®addr, 1, data, length, MS2ST(timeout));
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return chibios_to_qmk(&status);
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i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout) {
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i2c_address = devaddr;
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i2cStart(&I2C_DRIVER, &i2cconfig);
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msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), ®addr, 1, data, length, MS2ST(timeout));
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return chibios_to_qmk(&status);
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}
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void i2c_stop(void)
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{
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i2cStop(&I2C_DRIVER);
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}
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void i2c_stop(void) { i2cStop(&I2C_DRIVER); }
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@ -27,84 +27,83 @@
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#include "ch.h"
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#include <hal.h>
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#if defined(STM32F1XX) || defined(STM32F1xx) || defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32L0xx) || defined(STM32L1xx)
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#define USE_I2CV1
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# define USE_I2CV1
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#endif
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#ifdef I2C1_BANK
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#define I2C1_SCL_BANK I2C1_BANK
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#define I2C1_SDA_BANK I2C1_BANK
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# define I2C1_SCL_BANK I2C1_BANK
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# define I2C1_SDA_BANK I2C1_BANK
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#endif
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#ifndef I2C1_SCL_BANK
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#define I2C1_SCL_BANK GPIOB
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# define I2C1_SCL_BANK GPIOB
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#endif
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#ifndef I2C1_SDA_BANK
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#define I2C1_SDA_BANK GPIOB
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# define I2C1_SDA_BANK GPIOB
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#endif
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#ifndef I2C1_SCL
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#define I2C1_SCL 6
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# define I2C1_SCL 6
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#endif
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#ifndef I2C1_SDA
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#define I2C1_SDA 7
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# define I2C1_SDA 7
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#endif
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#ifdef USE_I2CV1
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#ifndef I2C1_OPMODE
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#define I2C1_OPMODE OPMODE_I2C
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#endif
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#ifndef I2C1_CLOCK_SPEED
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#define I2C1_CLOCK_SPEED 100000 /* 400000 */
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#endif
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#ifndef I2C1_DUTY_CYCLE
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#define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */
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#endif
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# ifndef I2C1_OPMODE
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# define I2C1_OPMODE OPMODE_I2C
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# endif
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# ifndef I2C1_CLOCK_SPEED
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# define I2C1_CLOCK_SPEED 100000 /* 400000 */
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# endif
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# ifndef I2C1_DUTY_CYCLE
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# define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */
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# endif
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#else
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// The default PAL alternate modes are used to signal that the pins are used for I2C
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#ifndef I2C1_SCL_PAL_MODE
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#define I2C1_SCL_PAL_MODE 4
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#endif
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#ifndef I2C1_SDA_PAL_MODE
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#define I2C1_SDA_PAL_MODE 4
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#endif
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// The default PAL alternate modes are used to signal that the pins are used for I2C
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# ifndef I2C1_SCL_PAL_MODE
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# define I2C1_SCL_PAL_MODE 4
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# endif
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# ifndef I2C1_SDA_PAL_MODE
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# define I2C1_SDA_PAL_MODE 4
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# endif
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// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
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// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
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#ifndef I2C1_TIMINGR_PRESC
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#define I2C1_TIMINGR_PRESC 15U
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#endif
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#ifndef I2C1_TIMINGR_SCLDEL
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#define I2C1_TIMINGR_SCLDEL 4U
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#endif
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#ifndef I2C1_TIMINGR_SDADEL
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#define I2C1_TIMINGR_SDADEL 2U
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#endif
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#ifndef I2C1_TIMINGR_SCLH
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#define I2C1_TIMINGR_SCLH 15U
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#endif
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#ifndef I2C1_TIMINGR_SCLL
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#define I2C1_TIMINGR_SCLL 21U
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#endif
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// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
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// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
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# ifndef I2C1_TIMINGR_PRESC
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# define I2C1_TIMINGR_PRESC 15U
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# endif
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# ifndef I2C1_TIMINGR_SCLDEL
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# define I2C1_TIMINGR_SCLDEL 4U
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# endif
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# ifndef I2C1_TIMINGR_SDADEL
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# define I2C1_TIMINGR_SDADEL 2U
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# endif
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# ifndef I2C1_TIMINGR_SCLH
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# define I2C1_TIMINGR_SCLH 15U
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# endif
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# ifndef I2C1_TIMINGR_SCLL
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# define I2C1_TIMINGR_SCLL 21U
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# endif
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#endif
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#ifndef I2C_DRIVER
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#define I2C_DRIVER I2CD1
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# define I2C_DRIVER I2CD1
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#endif
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typedef int16_t i2c_status_t;
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#define I2C_STATUS_SUCCESS (0)
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#define I2C_STATUS_ERROR (-1)
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#define I2C_STATUS_ERROR (-1)
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#define I2C_STATUS_TIMEOUT (-2)
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void i2c_init(void);
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void i2c_init(void);
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i2c_status_t i2c_start(uint8_t address);
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i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout);
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i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout);
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i2c_status_t i2c_transmit_receive(uint8_t address, uint8_t * tx_body, uint16_t tx_length, uint8_t * rx_body, uint16_t rx_length);
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i2c_status_t i2c_transmit_receive(uint8_t address, uint8_t* tx_body, uint16_t tx_length, uint8_t* rx_body, uint16_t rx_length);
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i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
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i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
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void i2c_stop(void);
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void i2c_stop(void);
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