Normalize line endings
This commit is contained in:
Fred Sundvik
parent
de58ec9738
commit
a5b1af4999
39 changed files with 6322 additions and 6322 deletions
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@ -1,156 +1,156 @@
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;---------------------------------------------------------------------------;
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; Software implemented UART module ;
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; (C)ChaN, 2005 (http://elm-chan.org/) ;
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;---------------------------------------------------------------------------;
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; Bit rate settings:
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;
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; 1MHz 2MHz 4MHz 6MHz 8MHz 10MHz 12MHz 16MHz 20MHz
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; 2.4kbps 138 - - - - - - - -
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; 4.8kbps 68 138 - - - - - - -
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; 9.6kbps 33 68 138 208 - - - - -
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; 19.2kbps - 33 68 102 138 173 208 - -
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; 38.4kbps - - 33 50 68 85 102 138 172
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; 57.6kbps - - 21 33 44 56 68 91 114
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; 115.2kbps - - - - 21 27 33 44 56
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.nolist
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#include <avr/io.h>
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.list
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#define BPS 102 /* Bit delay. (see above table) */
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#define BIDIR 0 /* 0:Separated Tx/Rx, 1:Shared Tx/Rx */
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#define OUT_1 sbi _SFR_IO_ADDR(SUART_OUT_PORT), SUART_OUT_BIT /* Output 1 */
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#define OUT_0 cbi _SFR_IO_ADDR(SUART_OUT_PORT), SUART_OUT_BIT /* Output 0 */
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#define SKIP_IN_1 sbis _SFR_IO_ADDR(SUART_IN_PIN), SUART_IN_BIT /* Skip if 1 */
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#define SKIP_IN_0 sbic _SFR_IO_ADDR(SUART_IN_PIN), SUART_IN_BIT /* Skip if 0 */
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#ifdef SPM_PAGESIZE
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.macro _LPMI reg
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lpm \reg, Z+
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.endm
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.macro _MOVW dh,dl, sh,sl
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movw \dl, \sl
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.endm
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#else
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.macro _LPMI reg
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lpm
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mov \reg, r0
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adiw ZL, 1
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.endm
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.macro _MOVW dh,dl, sh,sl
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mov \dl, \sl
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mov \dh, \sh
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.endm
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#endif
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;---------------------------------------------------------------------------;
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; Transmit a byte in serial format of N81
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;
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;Prototype: void xmit (uint8_t data);
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;Size: 16 words
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.global xmit
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.func xmit
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xmit:
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#if BIDIR
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ldi r23, BPS-1 ;Pre-idle time for bidirectional data line
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5: dec r23 ;
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brne 5b ;/
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#endif
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in r0, _SFR_IO_ADDR(SREG) ;Save flags
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com r24 ;C = start bit
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ldi r25, 10 ;Bit counter
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cli ;Start critical section
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1: ldi r23, BPS-1 ;----- Bit transferring loop
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2: dec r23 ;Wait for a bit time
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brne 2b ;/
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brcs 3f ;MISO = bit to be sent
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OUT_1 ;
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3: brcc 4f ;
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OUT_0 ;/
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4: lsr r24 ;Get next bit into C
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dec r25 ;All bits sent?
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brne 1b ; no, coutinue
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out _SFR_IO_ADDR(SREG), r0 ;End of critical section
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ret
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.endfunc
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;---------------------------------------------------------------------------;
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; Receive a byte
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;
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;Prototype: uint8_t rcvr (void);
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;Size: 19 words
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.global rcvr
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.func rcvr
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rcvr:
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in r0, _SFR_IO_ADDR(SREG) ;Save flags
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ldi r24, 0x80 ;Receiving shift reg
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cli ;Start critical section
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1: SKIP_IN_1 ;Wait for idle
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rjmp 1b
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2: SKIP_IN_0 ;Wait for start bit
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rjmp 2b
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ldi r25, BPS/2 ;Wait for half bit time
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3: dec r25
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brne 3b
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4: ldi r25, BPS ;----- Bit receiving loop
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5: dec r25 ;Wait for a bit time
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brne 5b ;/
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lsr r24 ;Next bit
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SKIP_IN_0 ;Get a data bit into r24.7
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ori r24, 0x80
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brcc 4b ;All bits received? no, continue
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out _SFR_IO_ADDR(SREG), r0 ;End of critical section
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ret
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.endfunc
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; Not wait for start bit. This should be called after detecting start bit.
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.global recv
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.func recv
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recv:
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in r0, _SFR_IO_ADDR(SREG) ;Save flags
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ldi r24, 0x80 ;Receiving shift reg
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cli ;Start critical section
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;1: SKIP_IN_1 ;Wait for idle
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; rjmp 1b
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;2: SKIP_IN_0 ;Wait for start bit
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; rjmp 2b
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ldi r25, BPS/2 ;Wait for half bit time
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3: dec r25
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brne 3b
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4: ldi r25, BPS ;----- Bit receiving loop
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5: dec r25 ;Wait for a bit time
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brne 5b ;/
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lsr r24 ;Next bit
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SKIP_IN_0 ;Get a data bit into r24.7
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ori r24, 0x80
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brcc 4b ;All bits received? no, continue
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ldi r25, BPS/2 ;Wait for half bit time
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6: dec r25
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brne 6b
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7: SKIP_IN_1 ;Wait for stop bit
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rjmp 7b
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out _SFR_IO_ADDR(SREG), r0 ;End of critical section
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ret
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.endfunc
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;---------------------------------------------------------------------------;
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; Software implemented UART module ;
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; (C)ChaN, 2005 (http://elm-chan.org/) ;
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;---------------------------------------------------------------------------;
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; Bit rate settings:
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;
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; 1MHz 2MHz 4MHz 6MHz 8MHz 10MHz 12MHz 16MHz 20MHz
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; 2.4kbps 138 - - - - - - - -
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; 4.8kbps 68 138 - - - - - - -
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; 9.6kbps 33 68 138 208 - - - - -
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; 19.2kbps - 33 68 102 138 173 208 - -
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; 38.4kbps - - 33 50 68 85 102 138 172
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; 57.6kbps - - 21 33 44 56 68 91 114
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; 115.2kbps - - - - 21 27 33 44 56
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.nolist
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#include <avr/io.h>
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.list
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#define BPS 102 /* Bit delay. (see above table) */
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#define BIDIR 0 /* 0:Separated Tx/Rx, 1:Shared Tx/Rx */
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#define OUT_1 sbi _SFR_IO_ADDR(SUART_OUT_PORT), SUART_OUT_BIT /* Output 1 */
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#define OUT_0 cbi _SFR_IO_ADDR(SUART_OUT_PORT), SUART_OUT_BIT /* Output 0 */
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#define SKIP_IN_1 sbis _SFR_IO_ADDR(SUART_IN_PIN), SUART_IN_BIT /* Skip if 1 */
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#define SKIP_IN_0 sbic _SFR_IO_ADDR(SUART_IN_PIN), SUART_IN_BIT /* Skip if 0 */
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#ifdef SPM_PAGESIZE
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.macro _LPMI reg
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lpm \reg, Z+
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.endm
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.macro _MOVW dh,dl, sh,sl
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movw \dl, \sl
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.endm
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#else
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.macro _LPMI reg
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lpm
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mov \reg, r0
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adiw ZL, 1
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.endm
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.macro _MOVW dh,dl, sh,sl
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mov \dl, \sl
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mov \dh, \sh
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.endm
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#endif
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;---------------------------------------------------------------------------;
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; Transmit a byte in serial format of N81
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;
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;Prototype: void xmit (uint8_t data);
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;Size: 16 words
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.global xmit
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.func xmit
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xmit:
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#if BIDIR
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ldi r23, BPS-1 ;Pre-idle time for bidirectional data line
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5: dec r23 ;
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brne 5b ;/
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#endif
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in r0, _SFR_IO_ADDR(SREG) ;Save flags
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com r24 ;C = start bit
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ldi r25, 10 ;Bit counter
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cli ;Start critical section
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1: ldi r23, BPS-1 ;----- Bit transferring loop
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2: dec r23 ;Wait for a bit time
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brne 2b ;/
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brcs 3f ;MISO = bit to be sent
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OUT_1 ;
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3: brcc 4f ;
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OUT_0 ;/
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4: lsr r24 ;Get next bit into C
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dec r25 ;All bits sent?
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brne 1b ; no, coutinue
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out _SFR_IO_ADDR(SREG), r0 ;End of critical section
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ret
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.endfunc
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;---------------------------------------------------------------------------;
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; Receive a byte
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;
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;Prototype: uint8_t rcvr (void);
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;Size: 19 words
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.global rcvr
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.func rcvr
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rcvr:
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in r0, _SFR_IO_ADDR(SREG) ;Save flags
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ldi r24, 0x80 ;Receiving shift reg
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cli ;Start critical section
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1: SKIP_IN_1 ;Wait for idle
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rjmp 1b
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2: SKIP_IN_0 ;Wait for start bit
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rjmp 2b
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ldi r25, BPS/2 ;Wait for half bit time
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3: dec r25
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brne 3b
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4: ldi r25, BPS ;----- Bit receiving loop
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5: dec r25 ;Wait for a bit time
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brne 5b ;/
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lsr r24 ;Next bit
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SKIP_IN_0 ;Get a data bit into r24.7
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ori r24, 0x80
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brcc 4b ;All bits received? no, continue
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out _SFR_IO_ADDR(SREG), r0 ;End of critical section
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ret
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.endfunc
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; Not wait for start bit. This should be called after detecting start bit.
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.global recv
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.func recv
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recv:
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in r0, _SFR_IO_ADDR(SREG) ;Save flags
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ldi r24, 0x80 ;Receiving shift reg
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cli ;Start critical section
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;1: SKIP_IN_1 ;Wait for idle
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; rjmp 1b
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;2: SKIP_IN_0 ;Wait for start bit
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; rjmp 2b
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ldi r25, BPS/2 ;Wait for half bit time
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3: dec r25
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brne 3b
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4: ldi r25, BPS ;----- Bit receiving loop
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5: dec r25 ;Wait for a bit time
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brne 5b ;/
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lsr r24 ;Next bit
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SKIP_IN_0 ;Get a data bit into r24.7
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ori r24, 0x80
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brcc 4b ;All bits received? no, continue
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ldi r25, BPS/2 ;Wait for half bit time
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6: dec r25
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brne 6b
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7: SKIP_IN_1 ;Wait for stop bit
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rjmp 7b
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out _SFR_IO_ADDR(SREG), r0 ;End of critical section
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ret
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.endfunc
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@ -1,8 +1,8 @@
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#ifndef SUART
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#define SUART
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void xmit(uint8_t);
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uint8_t rcvr(void);
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uint8_t recv(void);
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#endif /* SUART */
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#ifndef SUART
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#define SUART
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void xmit(uint8_t);
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uint8_t rcvr(void);
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uint8_t recv(void);
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#endif /* SUART */
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@ -1,159 +1,159 @@
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/* This is from http://www.mtcnet.net/~henryvm/wdt/ */
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#ifndef _AVR_WD_H_
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#define _AVR_WD_H_
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#include <avr/io.h>
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/*
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Copyright (c) 2009, Curt Van Maanen
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Permission to use, copy, modify, and/or distribute this software for any
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purpose with or without fee is hereby granted, provided that the above
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copyright notice and this permission notice appear in all copies.
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THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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include usage-
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#include "wd.h" //if in same directory as project
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#include <avr/wd.h> //if wd.h is in avr directory
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set watchdog modes and prescale
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usage-
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WD_SET(mode,[timeout]); //prescale always set
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modes-
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WD_OFF disabled
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WD_RST normal reset mode
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WD_IRQ interrupt only mode (if supported)
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WD_RST_IRQ interrupt+reset mode (if supported)
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timeout-
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WDTO_15MS default if no timeout provided
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WDTO_30MS
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WDTO_60MS
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WDTO_120MS
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WDTO_250MS
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WDTO_500MS
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WDTO_1S
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WDTO_2S
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WDTO_4S (if supported)
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WDTO_8S (if supported)
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examples-
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WD_SET(WD_RST,WDTO_1S); //reset mode, 1s timeout
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WD_SET(WD_OFF); //watchdog disabled (if not fused on)
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WD_SET(WD_RST); //reset mode, 15ms (default timeout)
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WD_SET(WD_IRQ,WDTO_120MS); //interrupt only mode, 120ms timeout
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WD_SET(WD_RST_IRQ,WDTO_2S); //interrupt+reset mode, 2S timeout
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for enhanced watchdogs, if the watchdog is not being used WDRF should be
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cleared on every power up or reset, along with disabling the watchdog-
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WD_DISABLE(); //clear WDRF, then turn off watchdog
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*/
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//reset registers to the same name (MCUCSR)
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#if !defined(MCUCSR)
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#define MCUCSR MCUSR
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#endif
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//watchdog registers to the same name (WDTCSR)
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#if !defined(WDTCSR)
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#define WDTCSR WDTCR
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#endif
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//if enhanced watchdog, define irq values, create disable macro
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#if defined(WDIF)
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#define WD_IRQ 0xC0
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#define WD_RST_IRQ 0xC8
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#define WD_DISABLE() do{ \
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MCUCSR &= ~(1<<WDRF); \
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WD_SET(WD_OFF); \
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}while(0)
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#endif
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//all watchdogs
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#define WD_RST 8
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#define WD_OFF 0
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//prescale values
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#define WDTO_15MS 0
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#define WDTO_30MS 1
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#define WDTO_60MS 2
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#define WDTO_120MS 3
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#define WDTO_250MS 4
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#define WDTO_500MS 5
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#define WDTO_1S 6
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#define WDTO_2S 7
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//prescale values for avrs with WDP3
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#if defined(WDP3)
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#define WDTO_4S 0x20
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#define WDTO_8S 0x21
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#endif
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//watchdog reset
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#define WDR() __asm__ __volatile__("wdr")
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//avr reset using watchdog
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#define WD_AVR_RESET() do{ \
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__asm__ __volatile__("cli"); \
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WD_SET_UNSAFE(WD_RST); \
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while(1); \
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}while(0)
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/*set the watchdog-
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1. save SREG
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2. turn off irq's
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3. reset watchdog timer
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4. enable watchdog change
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5. write watchdog value
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6. restore SREG (restoring irq status)
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*/
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#define WD_SET(val,...) \
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__asm__ __volatile__( \
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"in __tmp_reg__,__SREG__" "\n\t" \
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"cli" "\n\t" \
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"wdr" "\n\t" \
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"sts %[wdreg],%[wden]" "\n\t" \
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"sts %[wdreg],%[wdval]" "\n\t" \
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"out __SREG__,__tmp_reg__" "\n\t" \
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: \
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: [wdreg] "M" (&WDTCSR), \
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[wden] "r" ((uint8_t)(0x18)), \
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[wdval] "r" ((uint8_t)(val|(__VA_ARGS__+0))) \
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: "r0" \
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)
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/*set the watchdog when I bit in SREG known to be clear-
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1. reset watchdog timer
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2. enable watchdog change
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5. write watchdog value
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*/
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#define WD_SET_UNSAFE(val,...) \
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__asm__ __volatile__( \
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"wdr" "\n\t" \
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"sts %[wdreg],%[wden]" "\n\t" \
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"sts %[wdreg],%[wdval]" "\n\t" \
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: \
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: [wdreg] "M" (&WDTCSR), \
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[wden] "r" ((uint8_t)(0x18)), \
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[wdval] "r" ((uint8_t)(val|(__VA_ARGS__+0))) \
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)
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//for compatibility with avr/wdt.h
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#define wdt_enable(val) WD_SET(WD_RST,val)
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#define wdt_disable() WD_SET(WD_OFF)
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#endif /* _AVR_WD_H_ */
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/* This is from http://www.mtcnet.net/~henryvm/wdt/ */
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#ifndef _AVR_WD_H_
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||||
#define _AVR_WD_H_
|
||||
|
||||
#include <avr/io.h>
|
||||
|
||||
/*
|
||||
Copyright (c) 2009, Curt Van Maanen
|
||||
|
||||
Permission to use, copy, modify, and/or distribute this software for any
|
||||
purpose with or without fee is hereby granted, provided that the above
|
||||
copyright notice and this permission notice appear in all copies.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
|
||||
|
||||
include usage-
|
||||
#include "wd.h" //if in same directory as project
|
||||
#include <avr/wd.h> //if wd.h is in avr directory
|
||||
|
||||
set watchdog modes and prescale
|
||||
|
||||
usage-
|
||||
WD_SET(mode,[timeout]); //prescale always set
|
||||
|
||||
modes-
|
||||
WD_OFF disabled
|
||||
WD_RST normal reset mode
|
||||
WD_IRQ interrupt only mode (if supported)
|
||||
WD_RST_IRQ interrupt+reset mode (if supported)
|
||||
|
||||
timeout-
|
||||
WDTO_15MS default if no timeout provided
|
||||
WDTO_30MS
|
||||
WDTO_60MS
|
||||
WDTO_120MS
|
||||
WDTO_250MS
|
||||
WDTO_500MS
|
||||
WDTO_1S
|
||||
WDTO_2S
|
||||
WDTO_4S (if supported)
|
||||
WDTO_8S (if supported)
|
||||
|
||||
examples-
|
||||
WD_SET(WD_RST,WDTO_1S); //reset mode, 1s timeout
|
||||
WD_SET(WD_OFF); //watchdog disabled (if not fused on)
|
||||
WD_SET(WD_RST); //reset mode, 15ms (default timeout)
|
||||
WD_SET(WD_IRQ,WDTO_120MS); //interrupt only mode, 120ms timeout
|
||||
WD_SET(WD_RST_IRQ,WDTO_2S); //interrupt+reset mode, 2S timeout
|
||||
|
||||
|
||||
for enhanced watchdogs, if the watchdog is not being used WDRF should be
|
||||
cleared on every power up or reset, along with disabling the watchdog-
|
||||
WD_DISABLE(); //clear WDRF, then turn off watchdog
|
||||
|
||||
*/
|
||||
|
||||
//reset registers to the same name (MCUCSR)
|
||||
#if !defined(MCUCSR)
|
||||
#define MCUCSR MCUSR
|
||||
#endif
|
||||
|
||||
//watchdog registers to the same name (WDTCSR)
|
||||
#if !defined(WDTCSR)
|
||||
#define WDTCSR WDTCR
|
||||
#endif
|
||||
|
||||
//if enhanced watchdog, define irq values, create disable macro
|
||||
#if defined(WDIF)
|
||||
#define WD_IRQ 0xC0
|
||||
#define WD_RST_IRQ 0xC8
|
||||
#define WD_DISABLE() do{ \
|
||||
MCUCSR &= ~(1<<WDRF); \
|
||||
WD_SET(WD_OFF); \
|
||||
}while(0)
|
||||
#endif
|
||||
|
||||
//all watchdogs
|
||||
#define WD_RST 8
|
||||
#define WD_OFF 0
|
||||
|
||||
//prescale values
|
||||
#define WDTO_15MS 0
|
||||
#define WDTO_30MS 1
|
||||
#define WDTO_60MS 2
|
||||
#define WDTO_120MS 3
|
||||
#define WDTO_250MS 4
|
||||
#define WDTO_500MS 5
|
||||
#define WDTO_1S 6
|
||||
#define WDTO_2S 7
|
||||
|
||||
//prescale values for avrs with WDP3
|
||||
#if defined(WDP3)
|
||||
#define WDTO_4S 0x20
|
||||
#define WDTO_8S 0x21
|
||||
#endif
|
||||
|
||||
//watchdog reset
|
||||
#define WDR() __asm__ __volatile__("wdr")
|
||||
|
||||
//avr reset using watchdog
|
||||
#define WD_AVR_RESET() do{ \
|
||||
__asm__ __volatile__("cli"); \
|
||||
WD_SET_UNSAFE(WD_RST); \
|
||||
while(1); \
|
||||
}while(0)
|
||||
|
||||
/*set the watchdog-
|
||||
1. save SREG
|
||||
2. turn off irq's
|
||||
3. reset watchdog timer
|
||||
4. enable watchdog change
|
||||
5. write watchdog value
|
||||
6. restore SREG (restoring irq status)
|
||||
*/
|
||||
#define WD_SET(val,...) \
|
||||
__asm__ __volatile__( \
|
||||
"in __tmp_reg__,__SREG__" "\n\t" \
|
||||
"cli" "\n\t" \
|
||||
"wdr" "\n\t" \
|
||||
"sts %[wdreg],%[wden]" "\n\t" \
|
||||
"sts %[wdreg],%[wdval]" "\n\t" \
|
||||
"out __SREG__,__tmp_reg__" "\n\t" \
|
||||
: \
|
||||
: [wdreg] "M" (&WDTCSR), \
|
||||
[wden] "r" ((uint8_t)(0x18)), \
|
||||
[wdval] "r" ((uint8_t)(val|(__VA_ARGS__+0))) \
|
||||
: "r0" \
|
||||
)
|
||||
|
||||
/*set the watchdog when I bit in SREG known to be clear-
|
||||
1. reset watchdog timer
|
||||
2. enable watchdog change
|
||||
5. write watchdog value
|
||||
*/
|
||||
#define WD_SET_UNSAFE(val,...) \
|
||||
__asm__ __volatile__( \
|
||||
"wdr" "\n\t" \
|
||||
"sts %[wdreg],%[wden]" "\n\t" \
|
||||
"sts %[wdreg],%[wdval]" "\n\t" \
|
||||
: \
|
||||
: [wdreg] "M" (&WDTCSR), \
|
||||
[wden] "r" ((uint8_t)(0x18)), \
|
||||
[wdval] "r" ((uint8_t)(val|(__VA_ARGS__+0))) \
|
||||
)
|
||||
|
||||
|
||||
//for compatibility with avr/wdt.h
|
||||
#define wdt_enable(val) WD_SET(WD_RST,val)
|
||||
#define wdt_disable() WD_SET(WD_OFF)
|
||||
|
||||
|
||||
#endif /* _AVR_WD_H_ */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue