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Clean up APA102 config and add DD mapping (#20159)

This commit is contained in:
Ryan 2023-03-20 08:12:19 +11:00 committed by GitHub
parent 3c144fac5e
commit 65a80f411f
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GPG key ID: 4AEE18F83AFDEB23
41 changed files with 106 additions and 53 deletions

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@ -23,8 +23,6 @@
#define ADC_PIN A0
#define RGB_CI_PIN A2
#define SOLENOID_PIN B12
#define SOLENOID_PINS { B12, B13, B14, B15 }
#define SOLENOID_PINS_ACTIVE_STATE { high, high, low }

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@ -10,5 +10,9 @@
},
"rgblight": {
"pin": "A1"
},
"apa102": {
"data_pin": "A1",
"clock_pin": "A2"
}
}

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@ -23,8 +23,6 @@
#define ADC_PIN A0
#define RGB_CI_PIN A2
#define SOLENOID_PIN B12
#define SOLENOID_PINS { B12, B13, B14, B15 }
#define SOLENOID_PINS_ACTIVE_STATE { high, high, low }

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@ -11,5 +11,9 @@
},
"rgblight": {
"pin": "A1"
},
"apa102": {
"data_pin": "A1",
"clock_pin": "A2"
}
}

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@ -23,8 +23,6 @@
#define ADC_PIN A0
#define RGB_CI_PIN A2
#define SOLENOID_PIN B12
#define SOLENOID_PINS { B12, B13, B14, B15 }
#define SOLENOID_PINS_ACTIVE_STATE { high, high, low }

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@ -10,5 +10,9 @@
},
"rgblight": {
"pin": "A1"
},
"apa102": {
"data_pin": "A1",
"clock_pin": "A2"
}
}

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@ -23,8 +23,6 @@
#define ADC_PIN A0
#define RGB_CI_PIN A2
#define SOLENOID_PIN B12
#define SOLENOID_PINS { B12, B13, B14, B15 }
#define SOLENOID_PINS_ACTIVE_STATE { high, high, low }

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@ -11,5 +11,9 @@
},
"rgblight": {
"pin": "A1"
},
"apa102": {
"data_pin": "A1",
"clock_pin": "A2"
}
}

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@ -21,5 +21,3 @@
#define BACKLIGHT_PWM_CHANNEL 1
#define ADC_PIN A0
#define RGB_CI_PIN A2

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@ -10,5 +10,9 @@
},
"rgblight": {
"pin": "A1"
},
"apa102": {
"data_pin": "A1",
"clock_pin": "A2"
}
}

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@ -22,8 +22,6 @@
#define ADC_PIN A0
#define RGB_CI_PIN A2
// This code does not fit into the really small flash of STM32F103x6 together
// with CONSOLE_ENABLE=yes, and the debugging console is probably more
// important for the "onekey" testing firmware. In a real firmware you may be

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@ -11,5 +11,9 @@
},
"rgblight": {
"pin": "A1"
},
"apa102": {
"data_pin": "A1",
"clock_pin": "A2"
}
}

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@ -21,5 +21,3 @@
#define BACKLIGHT_PWM_CHANNEL 1
#define ADC_PIN A0
#define RGB_CI_PIN A2

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@ -11,5 +11,9 @@
},
"rgblight": {
"pin": "A1"
},
"apa102": {
"data_pin": "A1",
"clock_pin": "A2"
}
}

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@ -16,9 +16,6 @@
#pragma once
#define RGB_CI_PIN B1
#define ADC_PIN F6
#define QMK_WAITING_TEST_BUSY_PIN F6

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@ -10,5 +10,9 @@
},
"rgblight": {
"pin": "F6"
},
"apa102": {
"data_pin": "F6",
"clock_pin": "B1"
}
}

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@ -11,7 +11,6 @@
#define BACKLIGHT_PAL_MODE 2
#define APA102_NOPS (100 / (1000000000L / (CPU_CLOCK / 4)))
#define RGB_CI_PIN B8
#define SOLENOID_PIN B12
#define SOLENOID_PINS { B12, B13, B14, B15 }

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@ -11,5 +11,9 @@
},
"rgblight": {
"pin": "A0"
},
"apa102": {
"data_pin": "A0",
"clock_pin": "B8"
}
}

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@ -11,7 +11,6 @@
#define BACKLIGHT_PAL_MODE 2
#define APA102_NOPS (100 / (1000000000L / (CPU_CLOCK / 4)))
#define RGB_CI_PIN B8
#define SOLENOID_PIN B12
#define SOLENOID_PINS { B12, B13, B14, B15 }

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@ -11,5 +11,9 @@
},
"rgblight": {
"pin": "A0"
},
"apa102": {
"data_pin": "A0",
"clock_pin": "B8"
}
}

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@ -7,8 +7,6 @@
#define BACKLIGHT_PWM_CHANNEL 3
#define BACKLIGHT_PAL_MODE 2
#define RGB_CI_PIN B13
#define ADC_PIN A0
#define SOLENOID_PINS { B12, B13, B14, B15 }

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@ -11,5 +11,9 @@
},
"rgblight": {
"pin": "A0"
},
"apa102": {
"data_pin": "A0",
"clock_pin": "B13"
}
}

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@ -7,6 +7,4 @@
#define BACKLIGHT_PWM_CHANNEL 3
#define BACKLIGHT_PAL_MODE 2
#define RGB_CI_PIN B13
#define ADC_PIN A0

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@ -11,5 +11,9 @@
},
"rgblight": {
"pin": "A0"
},
"apa102": {
"data_pin": "A0",
"clock_pin": "B13"
}
}

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@ -16,9 +16,6 @@
#pragma once
#define RGB_CI_PIN B1
#define ADC_PIN F6
#define QMK_WAITING_TEST_BUSY_PIN F6

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@ -10,5 +10,9 @@
},
"rgblight": {
"pin": "F6"
},
"apa102": {
"data_pin": "F6",
"clock_pin": "B1"
}
}

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@ -21,6 +21,4 @@
#define BACKLIGHT_PWM_CHANNEL 3
#define BACKLIGHT_PAL_MODE 2
#define RGB_CI_PIN B13
#define ADC_PIN A0

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@ -10,5 +10,9 @@
},
"rgblight": {
"pin": "A0"
},
"apa102": {
"data_pin": "A0",
"clock_pin": "B13"
}
}

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@ -20,8 +20,6 @@
#define BACKLIGHT_PWM_DRIVER PWMD5 /* GD32 numbering scheme starts from 0, TIMER4 on GD32 boards is TIMER5 on STM32 boards. */
#define BACKLIGHT_PWM_CHANNEL 2 /* GD32 numbering scheme starts from 0, Channel 1 on GD32 boards is Channel 2 on STM32 boards. */
#define RGB_CI_PIN B13
#define ADC_PIN A0
#define I2C1_CLOCK_SPEED 1000000 /* GD32VF103 supports fast mode plus. */

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@ -12,5 +12,9 @@
},
"rgblight": {
"pin": "A2"
},
"apa102": {
"data_pin": "A2",
"clock_pin": "B13"
}
}

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@ -22,5 +22,3 @@
#define BACKLIGHT_PAL_MODE 0
#define ADC_PIN A0
#define RGB_CI_PIN B13

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@ -11,5 +11,9 @@
},
"rgblight": {
"pin": "B15"
},
"apa102": {
"data_pin": "B15",
"clock_pin": "B13"
}
}

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@ -19,7 +19,5 @@
#define ADC_PIN F6
#define RGB_CI_PIN F7
#define QMK_WAITING_TEST_BUSY_PIN F6
#define QMK_WAITING_TEST_YIELD_PIN F7

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@ -11,5 +11,9 @@
},
"rgblight": {
"pin": "F6"
},
"apa102": {
"data_pin": "F6",
"clock_pin": "F7"
}
}

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@ -19,7 +19,5 @@
#define ADC_PIN F6
#define RGB_CI_PIN F7
#define QMK_WAITING_TEST_BUSY_PIN F6
#define QMK_WAITING_TEST_YIELD_PIN F7

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@ -11,5 +11,9 @@
},
"rgblight": {
"pin": "F6"
},
"apa102": {
"data_pin": "F6",
"clock_pin": "F7"
}
}