drashna/qmk_firmware
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions 2

[TractylM] Add F429 configuration

Browse source
This commit is contained in:
Drashna Jael're 2025-01-11 23:47:04 -08:00
parent 07811ea0a7
commit 5be3e0d303
Signed by: drashna
GPG key ID: DBA1FD3A860D1B11
11 changed files with 1027 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

23
keyboards/handwired/tractyl_manuform/5x6_right/f429/board.h Normal file
View file

@ -0,0 +1,23 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#include_next <board.h>
#undef STM32_HSECLK
#define STM32_HSECLK 8000000U
#undef STM32_LSECLK
#define STM32_LSECLK 32768U

85
keyboards/handwired/tractyl_manuform/5x6_right/f429/config.h Normal file
View file

@ -0,0 +1,85 @@
/*
Copyright 2012 Jun Wako <wakojun@gmail.com>
Copyright 2015 Jack Humbert
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
//#define USER_BUTTON_PIN A0
#define DEBUG_LED_PIN F6
// WS2812 RGB LED strip input and number of LEDs
#define WS2812_PWM_DRIVER PWMD3
#define WS2812_PWM_CHANNEL 1
#define WS2812_PWM_PAL_MODE 2
#define WS2812_PWM_DMA_STREAM STM32_DMA1_STREAM2
#define WS2812_PWM_DMA_CHANNEL 5
#define WS2812_EXTERNAL_PULLUP
#define BACKLIGHT_PWM_DRIVER PWMD8
#define BACKLIGHT_PWM_CHANNEL 3
#define BACKLIGHT_PAL_MODE 3
/* serial.c configuration for split keyboard */
#define SERIAL_USART_DRIVER SD1
#define SERIAL_USART_TX_PIN B6
#define SERIAL_USART_TX_PAL_MODE 7
#define SERIAL_USART_RX_PIN B7
#define SERIAL_USART_RX_PAL_MODE 7
#define SERIAL_USART_TIMEOUT 10
#define SERIAL_USART_SPEED (1 * 1024 * 1024)
#define SERIAL_USART_FULL_DUPLEX
/* i2c config for oleds */
#define I2C_DRIVER I2CD1
#define I2C1_SCL_PIN B8
#define I2C1_SCL_PAL_MODE 4
#define I2C1_SDA_PIN B9
#define I2C1_SDA_PAL_MODE 4
#define I2C1_CLOCK_SPEED 400000
#define I2C1_DUTY_CYCLE FAST_DUTY_CYCLE_16_9
/* spi config for eeprom and pmw3360 sensor */
#define SPI_DRIVER SPID1
#define SPI_SCK_PIN A5
#define SPI_SCK_PAL_MODE 5
#define SPI_MOSI_PIN A7
#define SPI_MOSI_PAL_MODE 5
#define SPI_MISO_PIN A6
#define SPI_MISO_PAL_MODE 5
#define EXTERNAL_FLASH_SPI_SLAVE_SELECT_PIN A4
#define EXTERNAL_FLASH_SPI_CLOCK_DIVISOR 4
#define EXTERNAL_FLASH_SIZE (8 * 1024 * 1024)
/* pmw3360 config */
#define POINTING_DEVICE_CS_PIN B5
#define POINTING_DEVICE_ROTATION_270
#undef ROTATIONAL_TRANSFORM_ANGLE
#define PMW33XX_SPI_DIVISOR 16
// lcd
#define DISPLAY_RST_PIN C9
#define DISPLAY_DC_PIN B12
#define DISPLAY_CS_PIN H12
#define DISPLAY_SPI_DIVIDER 4
#define DRV2605L_FB_ERM_LRA 0
#define DRV2605L_GREETING DRV2605L_EFFECT_750_MS_ALERT_100
#define DRV2605L_DEFAULT_MODE DRV2605L_EFFECT_BUZZ_1_100
#define DIP_SWITCH_PINS {G2, G3, G9, G10, D13, A0}

254
keyboards/handwired/tractyl_manuform/5x6_right/f429/f429.c Normal file
View file

@ -0,0 +1,254 @@
/* Copyright 2020 Christopher Courtney, aka Drashna Jael're (@drashna) <drashna@live.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "tractyl_manuform.h"
#ifdef USB_VBUS_PIN
bool usb_vbus_state(void) {
gpio_set_pin_input_low(USB_VBUS_PIN);
wait_us(5);
return gpio_read_pin(USB_VBUS_PIN);
}
#endif
void user_button_init(void) {
// Pin needs to be configured as input low
#ifdef USER_BUTTON_PIN
gpio_set_pin_input_high(USER_BUTTON_PIN);
#endif // USER_BUTTON_PIN
gpio_set_pin_output(F7);
gpio_write_pin_low(F7);
gpio_set_pin_output(F8);
gpio_write_pin_low(F8);
gpio_set_pin_output(F9);
gpio_write_pin_low(F9);
}
bool check_user_button_state(void) {
#ifdef DEBUG_LED_PIN
gpio_write_pin(DEBUG_LED_PIN, is_keyboard_master());
#endif
#ifdef USER_BUTTON_PIN
gpio_write_pin(F8, !gpio_read_pin(USER_BUTTON_PIN));
return !gpio_read_pin(USER_BUTTON_PIN);
#endif // USER_BUTTON_PIN
return false;
}
#if HAL_USE_SDRAM == TRUE
# pragma message "Configured to use SDRAM"
/* SDRAM bank base address.*/
# define SDRAM_BANK_ADDR ((uint32_t)0xD0000000)
/*
* FMC SDRAM Mode definition register defines
*/
# define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000)
# define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001)
# define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002)
# define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004)
# define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
# define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
# define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020)
# define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030)
# define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
# define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
# define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
/*
* FMC_ReadPipe_Delay
*/
# define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000)
# define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000)
# define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000)
# define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000)
/*
* FMC_Read_Burst
*/
# define FMC_Read_Burst_Disable ((uint32_t)0x00000000)
# define FMC_Read_Burst_Enable ((uint32_t)0x00001000)
# define FMC_Read_Burst_Mask ((uint32_t)0x00001000)
/*
* FMC_SDClock_Period
*/
# define FMC_SDClock_Disable ((uint32_t)0x00000000)
# define FMC_SDClock_Period_2 ((uint32_t)0x00000800)
# define FMC_SDClock_Period_3 ((uint32_t)0x00000C00)
# define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00)
/*
* FMC_ColumnBits_Number
*/
# define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000)
# define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001)
# define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002)
# define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003)
/*
* FMC_RowBits_Number
*/
# define FMC_RowBits_Number_11b ((uint32_t)0x00000000)
# define FMC_RowBits_Number_12b ((uint32_t)0x00000004)
# define FMC_RowBits_Number_13b ((uint32_t)0x00000008)
/*
* FMC_SDMemory_Data_Width
*/
# define FMC_SDMemory_Width_8b ((uint32_t)0x00000000)
# define FMC_SDMemory_Width_16b ((uint32_t)0x00000010)
# define FMC_SDMemory_Width_32b ((uint32_t)0x00000020)
/*
* FMC_InternalBank_Number
*/
# define FMC_InternalBank_Number_2 ((uint32_t)0x00000000)
# define FMC_InternalBank_Number_4 ((uint32_t)0x00000040)
/*
* FMC_CAS_Latency
*/
# define FMC_CAS_Latency_1 ((uint32_t)0x00000080)
# define FMC_CAS_Latency_2 ((uint32_t)0x00000100)
# define FMC_CAS_Latency_3 ((uint32_t)0x00000180)
/*
* FMC_Write_Protection
*/
# define FMC_Write_Protection_Disable ((uint32_t)0x00000000)
# define FMC_Write_Protection_Enable ((uint32_t)0x00000200)
# include "hal.h"
/*
* SDRAM driver configuration structure.
*/
static const SDRAMConfig sdram_cfg = {
// clang-format off
.sdcr = (uint32_t)(FMC_ColumnBits_Number_8b |
FMC_RowBits_Number_12b |
FMC_SDMemory_Width_16b |
FMC_InternalBank_Number_4 |
FMC_CAS_Latency_3 |
FMC_Write_Protection_Disable |
FMC_SDClock_Period_2 |
FMC_Read_Burst_Disable |
FMC_ReadPipe_Delay_1),
// clang-format on
.sdtr = (uint32_t)((2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles)
(7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns))
(4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns))
(7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns))
(2 << 16) | // FMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns))
(2 << 20) | // FMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns)
(2 << 24)), // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns)
// clang-format off
.sdcmr = (uint32_t)(((4 - 1) << 5) |
((FMC_SDCMR_MRD_BURST_LENGTH_2 |
FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |
FMC_SDCMR_MRD_CAS_LATENCY_3 |
FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |
FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9)),
// clang-format on
/* if (STM32_SYSCLK == 180000000) ->
64ms / 4096 = 15.625us
15.625us * 90MHz = 1406 - 20 = 1386 */
//.sdrtr = (1386 << 1),
.sdrtr = (uint32_t)(683 << 1),
};
/* SDRAM size, in bytes.*/
# define IS42S16400J_SIZE (8 * 1024 * 1024)
/*
* Erases the whole SDRAM bank.
*/
static void sdram_bulk_erase(void) {
volatile uint8_t *p = (volatile uint8_t *)SDRAM_BANK_ADDR;
volatile uint8_t *end = p + IS42S16400J_SIZE;
while (p < end)
*p++ = 0xFF;
}
# define FMC_SDRAM_D2_PIN D0
# define FMC_SDRAM_D3_PIN D1
# define FMC_SDRAM_D13_PIN D8
# define FMC_SDRAM_D14_PIN D9
# define FMC_SDRAM_D15_PIN D10
# define FMC_SDRAM_D0_PIN D14
# define FMC_SDRAM_D1_PIN D15
# define FMC_SDRAM_NBL0_PIN E0
# define FMC_SDRAM_NBL1_PIN E1
# define FMC_SDRAM_D4_PIN E7
# define FMC_SDRAM_D5_PIN E8
# define FMC_SDRAM_D6_PIN E9
# define FMC_SDRAM_D7_PIN E10
# define FMC_SDRAM_D8_PIN E11
# define FMC_SDRAM_D9_PIN E12
# define FMC_SDRAM_D10_PIN E13
# define FMC_SDRAM_D11_PIN E14
# define FMC_SDRAM_D12_PIN E15
# define FMC_SDRAM_A0_PIN F0
# define FMC_SDRAM_A1_PIN F1
# define FMC_SDRAM_A2_PIN F2
# define FMC_SDRAM_A3_PIN F3
# define FMC_SDRAM_A4_PIN F4
# define FMC_SDRAM_A5_PIN F5
# define FMC_SDRAM_SDNRAS_PIN F11
# define FMC_SDRAM_A6_PIN F12
# define FMC_SDRAM_A7_PIN F13
# define FMC_SDRAM_A8_PIN F14
# define FMC_SDRAM_A9_PIN F15
# define FMC_SDRAM_A10_PIN G0
# define FMC_SDRAM_A11_PIN G1
# define FMC_SDRAM_BA0_PIN G4
# define FMC_SDRAM_BA1_PIN G5
# define FMC_SDRAM_SDCLK_PIN G8
# define FMC_SDRAM_SDNCAS_PIN G15
# define FMC_SDRAM_SDNWE_PIN H5
# define FMC_SDRAM_SDNE1_PIN H6
# define FMC_SDRAM_SDCKE1_PIN H3
const pin_t fmc_sdram_pin_array[] = {
FMC_SDRAM_D0_PIN, FMC_SDRAM_D1_PIN, FMC_SDRAM_D2_PIN, FMC_SDRAM_D3_PIN, FMC_SDRAM_D4_PIN, FMC_SDRAM_D5_PIN, FMC_SDRAM_D6_PIN, FMC_SDRAM_D7_PIN, FMC_SDRAM_D8_PIN, FMC_SDRAM_D9_PIN, FMC_SDRAM_D10_PIN, FMC_SDRAM_D11_PIN, FMC_SDRAM_D12_PIN, FMC_SDRAM_A0_PIN, FMC_SDRAM_A1_PIN, FMC_SDRAM_A2_PIN, FMC_SDRAM_A3_PIN, FMC_SDRAM_A4_PIN, FMC_SDRAM_A5_PIN, FMC_SDRAM_A6_PIN, FMC_SDRAM_A7_PIN, FMC_SDRAM_A8_PIN, FMC_SDRAM_A9_PIN, FMC_SDRAM_A10_PIN, FMC_SDRAM_A11_PIN, FMC_SDRAM_BA0_PIN, FMC_SDRAM_BA1_PIN, FMC_SDRAM_SDNRAS_PIN, FMC_SDRAM_SDCLK_PIN, FMC_SDRAM_SDNCAS_PIN, FMC_SDRAM_SDNWE_PIN, FMC_SDRAM_SDNE1_PIN, FMC_SDRAM_SDCKE1_PIN, FMC_SDRAM_NBL0_PIN, FMC_SDRAM_NBL1_PIN,
};
void board_init(void) {
/*
* Initialise FSMC for SDRAM.
*/
for (uint8_t i = 0; i < ARRAY_SIZE(fmc_sdram_pin_array); i++) {
palSetLineMode(fmc_sdram_pin_array[i], (PAL_MODE_ALTERNATE(12) | PAL_STM32_OTYPE_PUSHPULL | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_PUPDR_FLOATING));
}
xprintf("SDRAM Init: Pins\n");
sdramInit();
sdramStart(&SDRAMD1, &sdram_cfg);
xprintf("SDRAM Init: Device\n");
xprintf("SDRAM Init: Full Erase Start\n");
sdram_bulk_erase();
xprintf("SDRAM Init: Full Erase Finish\n");
// // Board setup sets these pins as SPI, but we aren't using them as such.
// // So to prevent them from misbehaving, we need to set them to a different, non-spi mode.
// // This is a bit of a hack, but nothing else runs soon enough, without re-implementing spi_init().
// gpio_set_pin_input(A5);
// gpio_set_pin_input(A6);
// gpio_set_pin_input(A7);
}
#endif

36
keyboards/handwired/tractyl_manuform/5x6_right/f429/halconf.h Normal file
View file

@ -0,0 +1,36 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#define HAL_USE_SERIAL TRUE
#define SERIAL_BUFFERS_SIZE 256
#if defined(WS2812_PWM) || defined(BACKLIGHT_PWM)
# define HAL_USE_PWM TRUE
#endif // defined(WS2812_PWM) || defined(BACKLIGHT_PWM)
#if HAL_USE_SPI == TRUE
# define SPI_USE_WAIT TRUE
# define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
#endif
#ifdef AUDIO_DRIVER_DAC
# define HAL_USE_GPT TRUE
# define HAL_USE_DAC TRUE
#endif
#include_next <halconf.h>
#include "halconf_community.h"

187
keyboards/handwired/tractyl_manuform/5x6_right/f429/halconf_community.h Normal file
View file

@ -0,0 +1,187 @@
/*
ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef HALCONF_COMMUNITY_H
#define HALCONF_COMMUNITY_H
/**
* @brief Enables the community overlay.
*/
#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__)
#define HAL_USE_COMMUNITY TRUE
#endif
/**
* @brief Enables the FSMC subsystem.
*/
#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__)
#define HAL_USE_FSMC FALSE
#endif
/**
* @brief Enables the SDRAM subsystem.
*/
#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_SDRAM FALSE
#endif
/**
* @brief Enables the SRAM subsystem.
*/
#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_SRAM FALSE
#endif
/**
* @brief Enables the NAND subsystem.
*/
#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__)
#define HAL_USE_NAND FALSE
#endif
/**
* @brief Enables the 1-wire subsystem.
*/
#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__)
#define HAL_USE_ONEWIRE FALSE
#endif
/**
* @brief Enables the EICU subsystem.
*/
#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__)
#define HAL_USE_EICU FALSE
#endif
/**
* @brief Enables the CRC subsystem.
*/
#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__)
#define HAL_USE_CRC FALSE
#endif
/**
* @brief Enables the RNG subsystem.
*/
#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__)
#define HAL_USE_RNG FALSE
#endif
/**
* @brief Enables the EEPROM subsystem.
*/
#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__)
#define HAL_USE_EEPROM FALSE
#endif
/**
* @brief Enables the TIMCAP subsystem.
*/
#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__)
#define HAL_USE_TIMCAP FALSE
#endif
/**
* @brief Enables the TIMCAP subsystem.
*/
#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__)
#define HAL_USE_COMP FALSE
#endif
/**
* @brief Enables the QEI subsystem.
*/
#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__)
#define HAL_USE_QEI FALSE
#endif
/**
* @brief Enables the USBH subsystem.
*/
#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__)
#define HAL_USE_USBH FALSE
#endif
/**
* @brief Enables the USB_MSD subsystem.
*/
#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__)
#define HAL_USE_USB_MSD FALSE
#endif
/*===========================================================================*/
/* FSMCNAND driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define NAND_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* 1-wire driver related settings. */
/*===========================================================================*/
/**
* @brief Enables strong pull up feature.
* @note Disabling this option saves both code and data space.
*/
#define ONEWIRE_USE_STRONG_PULLUP FALSE
/**
* @brief Enables search ROM feature.
* @note Disabling this option saves both code and data space.
*/
#define ONEWIRE_USE_SEARCH_ROM TRUE
/*===========================================================================*/
/* QEI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables discard of overlow
*/
#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__)
#define QEI_USE_OVERFLOW_DISCARD FALSE
#endif
/**
* @brief Enables min max of overlow
*/
#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__)
#define QEI_USE_OVERFLOW_MINMAX FALSE
#endif
/*===========================================================================*/
/* EEProm driver related settings. */
/*===========================================================================*/
/**
* @brief Enables 24xx series I2C eeprom device driver.
* @note Disabling this option saves both code and data space.
*/
#define EEPROM_USE_EE24XX FALSE
/**
* @brief Enables 25xx series SPI eeprom device driver.
* @note Disabling this option saves both code and data space.
*/
#define EEPROM_USE_EE25XX FALSE
#endif /* HALCONF_COMMUNITY_H */
/** @} */

66
keyboards/handwired/tractyl_manuform/5x6_right/f429/keyboard.json Normal file
View file

@ -0,0 +1,66 @@
{
"keyboard_name": "Tractyl Manuform (5x6) WeAct STM32F429",
"audio": {
"driver": "dac_additive",
"power_control": {
"pin": "A3"
}
},
"backlight": {
"levels": 16,
"pin": "C8"
},
"bootloader": "stm32-dfu",
"build": {
"debounce_type": "asym_eager_defer_pk"
},
"diode_direction": "COL2ROW",
"encoder": {
"rotary": [
{"pin_a": "C1", "pin_b": "C0"}
]
},
"eeprom": {
"driver": "wear_leveling",
"wear_leveling": {
"driver": "spi_flash",
"backing_size": 16384,
"logical_size": 4096
}
},
"features": {
"console": true,
"haptic": true
},
"haptic": {
"driver": "drv2605l"
},
"matrix_pins": {
"cols": ["G12", "G11", "G12", "G13", "G14", "B5"],
"rows": ["D2", "D3", "D4", "D5", "D6", "D7"]
},
"processor": "STM32F429",
"rgblight": {
"led_count": 24,
"split": true
},
"split": {
"handedness": {
"pin": "B11"
},
"serial": {
"driver": "usart"
},
"transport": {
"sync": {
"activity": true,
"haptic": true,
"matrix_state": true
}
}
},
"ws2812": {
"driver": "pwm",
"pin": "C7"
}
}

89
keyboards/handwired/tractyl_manuform/5x6_right/f429/ld/STM32F429IGT6_SDRAM.ld Normal file
View file

@ -0,0 +1,89 @@
/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* ST32F429xI memory setup.
* Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0.
*/
MEMORY
{
flash0 (rx) : org = 0x08000000, len = 16k /* Sector 0 - Init code as ROM bootloader assumes application starts here */
flash1 (rx) : org = 0x08004000, len = 16k /* Sector 1 - Emulated eeprom */
flash2 (rx) : org = 0x08008000, len = 1M - 32k /* Sector 2..6 - Rest of firmware */
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */
ram1 : org = 0x20000000, len = 112k /* SRAM1 */
ram2 : org = 0x2001C000, len = 16k /* SRAM2 */
ram3 : org = 0x20020000, len = 64k /* SRAM3 */
ram4 : org = 0x10000000, len = 64k /* CCM SRAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0
ram7 : org = 0xD0000000, len = 8M /* SDRAM */
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash2);
REGION_ALIAS("XTORS_FLASH_LMA", flash2);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash2);
REGION_ALIAS("TEXT_FLASH_LMA", flash2);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash2);
REGION_ALIAS("RODATA_FLASH_LMA", flash2);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash2);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* RAM region to be used for SDRAM segment.*/
REGION_ALIAS("SDRAM_RAM", ram7);
/* Generic rules inclusion.*/
INCLUDE rules.ld

78
keyboards/handwired/tractyl_manuform/5x6_right/f429/mcuconf.h Normal file
View file

@ -0,0 +1,78 @@
/* Copyright 2020 Nick Brassel (tzarc)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#pragma once
#include_next <mcuconf.h>
#undef STM32_LSE_ENABLED
#define STM32_LSE_ENABLED TRUE
#undef STM32_RTCSEL
#define STM32_RTCSEL STM32_RTCSEL_LSE
#undef STM32_SERIAL_USE_USART1
#define STM32_SERIAL_USE_USART1 TRUE
#if HAL_USE_WDG == TRUE
# undef STM32_WDG_USE_IWDG
# define STM32_WDG_USE_IWDG TRUE
#endif
#if HAL_USE_I2C == TRUE
# undef STM32_I2C_USE_I2C1
# define STM32_I2C_USE_I2C1 TRUE
# undef STM32_I2C_BUSY_TIMEOUT
# define STM32_I2C_BUSY_TIMEOUT 10
# undef STM32_I2C_I2C1_RX_DMA_STREAM
# define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
# undef STM32_I2C_I2C1_TX_DMA_STREAM
# define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#endif // HAL_USE_I2C
#ifdef WS2812_PWM
# undef STM32_PWM_USE_TIM3
# define STM32_PWM_USE_TIM3 TRUE
#endif // WS2812_PWM
#ifdef BACKLIGHT_PWM
# undef STM32_PWM_USE_TIM8
# define STM32_PWM_USE_TIM8 TRUE
#endif
#if HAL_USE_SPI == TRUE
# undef STM32_SPI_USE_SPI1
# define STM32_SPI_USE_SPI1 TRUE
# undef STM32_SPI_SPI1_RX_DMA_STREAM
# define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
# undef STM32_SPI_SPI1_TX_DMA_STREAM
# define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#endif
#ifdef AUDIO_DRIVER_DAC
# undef STM32_DAC_USE_DAC1_CH1
# define STM32_DAC_USE_DAC1_CH1 TRUE
# undef STM32_DAC_USE_DAC1_CH2
# define STM32_DAC_USE_DAC1_CH2 TRUE
# undef STM32_GPT_USE_TIM6
# define STM32_GPT_USE_TIM6 TRUE
#endif // AUDIO_DRIVER_DAC
#include "mcuconf_community.h"

158
keyboards/handwired/tractyl_manuform/5x6_right/f429/mcuconf_community.h Normal file
View file

@ -0,0 +1,158 @@
/*
ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#define STM32_USE_DMA
/*
* FSMC driver system settings.
*/
#define STM32_FSMC_USE_FSMC1 TRUE
#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10
#define STM32_FSMC_DMA_CHN 0x03010201
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_NAND1 FALSE
#define STM32_NAND_USE_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0
#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")
/*
* FSMC SRAM driver system settings.
*/
#define STM32_SRAM_USE_SRAM1 FALSE
#define STM32_SRAM_USE_SRAM2 FALSE
#define STM32_SRAM_USE_SRAM3 FALSE
#define STM32_SRAM_USE_SRAM4 FALSE
/*
* FSMC SDRAM driver system settings.
*/
#define STM32_SDRAM_USE_SDRAM1 FALSE
#define STM32_SDRAM_USE_SDRAM2 TRUE
/*
* TIMCAP driver system settings.
*/
#define STM32_TIMCAP_USE_TIM1 TRUE
#define STM32_TIMCAP_USE_TIM2 FALSE
#define STM32_TIMCAP_USE_TIM3 TRUE
#define STM32_TIMCAP_USE_TIM4 TRUE
#define STM32_TIMCAP_USE_TIM5 TRUE
#define STM32_TIMCAP_USE_TIM8 TRUE
#define STM32_TIMCAP_USE_TIM9 TRUE
#define STM32_TIMCAP_TIM1_IRQ_PRIORITY 3
#define STM32_TIMCAP_TIM2_IRQ_PRIORITY 3
#define STM32_TIMCAP_TIM3_IRQ_PRIORITY 3
#define STM32_TIMCAP_TIM4_IRQ_PRIORITY 3
#define STM32_TIMCAP_TIM5_IRQ_PRIORITY 3
#define STM32_TIMCAP_TIM8_IRQ_PRIORITY 3
#define STM32_TIMCAP_TIM9_IRQ_PRIORITY 3
/*
* COMP driver system settings.
*/
#define STM32_COMP_USE_COMP1 TRUE
#define STM32_COMP_USE_COMP2 TRUE
#define STM32_COMP_USE_COMP3 TRUE
#define STM32_COMP_USE_COMP4 TRUE
#define STM32_COMP_USE_COMP5 TRUE
#define STM32_COMP_USE_COMP6 TRUE
#define STM32_COMP_USE_COMP7 TRUE
#define STM32_COMP_USE_INTERRUPTS TRUE
#define STM32_COMP_1_2_3_IRQ_PRIORITY 5
#define STM32_COMP_4_5_6_IRQ_PRIORITY 5
#define STM32_COMP_7_IRQ_PRIORITY 5
#if STM32_COMP_USE_INTERRUPTS
#define STM32_DISABLE_EXTI21_22_29_HANDLER
#define STM32_DISABLE_EXTI30_32_HANDLER
#define STM32_DISABLE_EXTI33_HANDLER
#endif
/*
* USBH driver system settings.
*/
#define STM32_OTG_FS_CHANNELS_NUMBER 8
#define STM32_OTG_HS_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG1 FALSE
#define STM32_OTG_FS_RXFIFO_SIZE 1024
#define STM32_OTG_FS_PTXFIFO_SIZE 128
#define STM32_OTG_FS_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG2 FALSE
#define STM32_OTG_HS_RXFIFO_SIZE 2048
#define STM32_OTG_HS_PTXFIFO_SIZE 1024
#define STM32_OTG_HS_NPTXFIFO_SIZE 1024
#define STM32_USBH_MIN_QSPACE 4
#define STM32_USBH_CHANNELS_NP 4
/*
* CRC driver system settings.
*/
#define STM32_CRC_USE_CRC1 TRUE
#define STM32_CRC_CRC1_DMA_IRQ_PRIORITY 1
#define STM32_CRC_CRC1_DMA_PRIORITY 2
#define STM32_CRC_CRC1_DMA_STREAM STM32_DMA1_STREAM2
#define CRCSW_USE_CRC1 FALSE
#define CRCSW_CRC32_TABLE TRUE
#define CRCSW_CRC16_TABLE TRUE
#define CRCSW_PROGRAMMABLE TRUE
/*
* EICU driver system settings.
*/
#define STM32_EICU_USE_TIM1 TRUE
#define STM32_EICU_USE_TIM2 FALSE
#define STM32_EICU_USE_TIM3 TRUE
#define STM32_EICU_USE_TIM4 TRUE
#define STM32_EICU_USE_TIM5 TRUE
#define STM32_EICU_USE_TIM8 TRUE
#define STM32_EICU_USE_TIM9 TRUE
#define STM32_EICU_USE_TIM10 TRUE
#define STM32_EICU_USE_TIM11 TRUE
#define STM32_EICU_USE_TIM12 TRUE
#define STM32_EICU_USE_TIM13 TRUE
#define STM32_EICU_USE_TIM14 TRUE
#define STM32_EICU_TIM1_IRQ_PRIORITY 7
#define STM32_EICU_TIM2_IRQ_PRIORITY 7
#define STM32_EICU_TIM3_IRQ_PRIORITY 7
#define STM32_EICU_TIM4_IRQ_PRIORITY 7
#define STM32_EICU_TIM5_IRQ_PRIORITY 7
#define STM32_EICU_TIM8_IRQ_PRIORITY 7
#define STM32_EICU_TIM9_IRQ_PRIORITY 7
#define STM32_EICU_TIM10_IRQ_PRIORITY 7
#define STM32_EICU_TIM11_IRQ_PRIORITY 7
#define STM32_EICU_TIM12_IRQ_PRIORITY 7
#define STM32_EICU_TIM13_IRQ_PRIORITY 7
#define STM32_EICU_TIM14_IRQ_PRIORITY 7
/*
* QEI driver system settings.
*/
#define STM32_QEI_USE_TIM1 TRUE
#define STM32_QEI_USE_TIM2 FALSE
#define STM32_QEI_USE_TIM3 TRUE
#define STM32_QEI_TIM1_IRQ_PRIORITY 3
#define STM32_QEI_TIM2_IRQ_PRIORITY 3
#define STM32_QEI_TIM3_IRQ_PRIORITY 3

50
keyboards/handwired/tractyl_manuform/5x6_right/f429/readme.md Normal file
View file

@ -0,0 +1,50 @@
A0 - Column 3
A1 - Column 4
A2 - Colume 5
A3 - Audio Enable
A4 - DAC Audio
A5 - DAC Aduio
A6 - Row 0
A7 - Row 1
A8 -
A9 - VBUS Sense -- Don't use - USART TX
A10 - USART RX (weak internal pullup)
A11 - USB D-
A12 - USB D+
A13 - SWD DIO
A14 - SWD CLK
A15 - Encoder Pin B
B0 - Row 4
B1 - Row 5
B2 - Boot1 - user LED
B3 - SPI SCK
B4 - SPI MISO
B5 - SPI MOSI
B6 - I2C SCL
B7 - I2C SDA
B8 - LCD Display CS Pin
B9 - Pointing Device CS Pin
B10 - Manual VBUS Detect Pin
B11 - Split Hand Pin
B12 - (weak internal pullup) - LCD Display DC Pin
B13 - LCD Display RST Pin
B14 -
B15 -
C0 - Encoder Pin A
C1 - Column 0
C2 - Column 1
C3 - Column 2
C4 - Row 2
C5 - Row 3
C6 - WS2812 PWM Pin
C7 - Backlight PWM Pin
C8 - TF Interface
C9 - TF Interface
C10 - TF Interface
C11 - TF Interface
C12 - TF Interface
C13 - User Button
C14 - LSE Crystal
C15 - LSE Crystal

1
keyboards/handwired/tractyl_manuform/5x6_right/f429/rules.mk Normal file
View file

@ -0,0 +1 @@
MCU_LDSCRIPT = STM32F429IGT6_SDRAM